Tabu search based cells placement in nanofabric architectures with restricted connectivity

New advances in nano-electronics have led to the introduction of CMOL (CMOS/Nano-devices hybrid) circuits which consists of an overlay of a nanowires over a CMOS stack. CMOL circuits can implement a netlist of NOR gates and Inverters using diode-like nanodevices. CMOL has inherently restricted connectivity due to limited nanowires length. Therefore connectivity of the circuit's elements is constrained to be within a certain radius, else an intermediary buffers are required. In this paper we present a Tabu search (TS) algorithm to address cells placement problem in CMOL. The Heuristic is engineered to provide feasible circuit implementations by efficient exploration of search space. Empirical results for ISCAS'89 benchmarks are compared with previous solutions using GA, MA, and LRMA heuristics. Results show that in almost all cases, TS exhibits more intelligent search of the solutions subspace, and is able to find better solutions. For all tested benchmarks over 90% reduction in average CPU processing time when compared with best published techniques was obtained.