{"title":"通过高精度TDC测量片上抖动","authors":"A. Garg, P. Dubey","doi":"10.1109/ISQED.2008.68","DOIUrl":null,"url":null,"abstract":"In high speed applications, ratio of total jitter to clock period is critical. It necessitates accurate measurement of Jitter. In this paper we describe an on- chip methodology to measure jitter in time domain, with resolutions up to 0.1 ps.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"On Chip Jitter Measurement through a High Accuracy TDC\",\"authors\":\"A. Garg, P. Dubey\",\"doi\":\"10.1109/ISQED.2008.68\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In high speed applications, ratio of total jitter to clock period is critical. It necessitates accurate measurement of Jitter. In this paper we describe an on- chip methodology to measure jitter in time domain, with resolutions up to 0.1 ps.\",\"PeriodicalId\":243121,\"journal\":{\"name\":\"9th International Symposium on Quality Electronic Design (isqed 2008)\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-03-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"9th International Symposium on Quality Electronic Design (isqed 2008)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED.2008.68\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"9th International Symposium on Quality Electronic Design (isqed 2008)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2008.68","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
On Chip Jitter Measurement through a High Accuracy TDC
In high speed applications, ratio of total jitter to clock period is critical. It necessitates accurate measurement of Jitter. In this paper we describe an on- chip methodology to measure jitter in time domain, with resolutions up to 0.1 ps.
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