256Kb CMNOS EPROM

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1984.1156664

Te-Long Chiu, Tsung-Ching Wu, G. Perlegos

{"title":"256Kb CMNOS EPROM","authors":"Te-Long Chiu, Tsung-Ching Wu, G. Perlegos","doi":"10.1109/ISSCC.1984.1156664","DOIUrl":null,"url":null,"abstract":"A 125ns, 50mW 256Kb EPROM featuring 12V-16V programming will be described. The design utilizes a 1.5μm N-well CMOS on epi technology resulting In a cell size of 37.5μm<sup>2</sup>and a die size of 180 mil ×180 mil.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"256Kb CMNOS EPROM\",\"authors\":\"Te-Long Chiu, Tsung-Ching Wu, G. Perlegos\",\"doi\":\"10.1109/ISSCC.1984.1156664\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 125ns, 50mW 256Kb EPROM featuring 12V-16V programming will be described. The design utilizes a 1.5μm N-well CMOS on epi technology resulting In a cell size of 37.5μm<sup>2</sup>and a die size of 180 mil ×180 mil.\",\"PeriodicalId\":260117,\"journal\":{\"name\":\"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1984.1156664\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1984.1156664","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

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摘要

一个125ns, 50mW 256Kb EPROM，具有12V-16V编程。该设计采用1.5μm n阱CMOS on epi技术，电池尺寸为37.5μm2，芯片尺寸为180 mil ×180 mil。

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256Kb CMNOS EPROM

A 125ns, 50mW 256Kb EPROM featuring 12V-16V programming will be described. The design utilizes a 1.5μm N-well CMOS on epi technology resulting In a cell size of 37.5μm²and a die size of 180 mil ×180 mil.

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1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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