在深亚微米CMOS技术模拟应用的高耐压ESD设计

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI:10.1109/CICC.2002.1012773

Chung-Hui Chen, Yean-Kuen Fang, Chien-Chun Tsai, S. Tu, Mark Chen, Mi-Chang Chang

{"title":"在深亚微米CMOS技术模拟应用的高耐压ESD设计","authors":"Chung-Hui Chen, Yean-Kuen Fang, Chien-Chun Tsai, S. Tu, Mark Chen, Mi-Chang Chang","doi":"10.1109/CICC.2002.1012773","DOIUrl":null,"url":null,"abstract":"A new high voltage tolerant (HVT) ESD design adopts one forward biased P+/N-well diode in series of one stacked NMOS to reduce the total capacitance and maintain the high ESD performance is proposed and implemented by 0.18 /spl mu/m CMOS technologies. The measured HBM and MM ESD levels of the HVT pin exceed 6 kV and 550 V, respectively, while the measured input capacitance is only 250 fF.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"High voltage tolerant ESD design for analog applications in deep submicron CMOS technologies\",\"authors\":\"Chung-Hui Chen, Yean-Kuen Fang, Chien-Chun Tsai, S. Tu, Mark Chen, Mi-Chang Chang\",\"doi\":\"10.1109/CICC.2002.1012773\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new high voltage tolerant (HVT) ESD design adopts one forward biased P+/N-well diode in series of one stacked NMOS to reduce the total capacitance and maintain the high ESD performance is proposed and implemented by 0.18 /spl mu/m CMOS technologies. The measured HBM and MM ESD levels of the HVT pin exceed 6 kV and 550 V, respectively, while the measured input capacitance is only 250 fF.\",\"PeriodicalId\":209025,\"journal\":{\"name\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"volume\":\"87 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2002.1012773\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2002.1012773","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

提出了一种新的高容压ESD设计方案，采用一个正偏P+/ n阱二极管串联在一个堆叠的NMOS上，以减小总电容并保持高ESD性能，并采用0.18 /spl mu/m CMOS技术实现。测量到的HVT引脚HBM和MM ESD电平分别超过6 kV和550 V，而测量到的输入电容仅为250 fF。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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High voltage tolerant ESD design for analog applications in deep submicron CMOS technologies

A new high voltage tolerant (HVT) ESD design adopts one forward biased P+/N-well diode in series of one stacked NMOS to reduce the total capacitance and maintain the high ESD performance is proposed and implemented by 0.18 /spl mu/m CMOS technologies. The measured HBM and MM ESD levels of the HVT pin exceed 6 kV and 550 V, respectively, while the measured input capacitance is only 250 fF.

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Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)

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