Test cost saving and challenges in the implementation of /spl times/6 and /spl times/8 parallel testing on freescale 16-bit HCS12 microcontroller product family

One of the pressing issues faced by the semiconductor industry today is the cost of testing, especially on the low cost and high volume microcontroller (MCU) supply to automotive market. This paper describes the general consideration and justification made on the investment of tester, handler and device interface board (DIB) to enable the /spl times/6 and /spl times/8 multi-site testing on the 80 and 112pin counts 16-bit HCS12 MCU in quad flat pack (QFP) package and the associate test cost reduction and tester saving estimation. Test issue encounter on the first spin of /spl times/6 and /spl times/8 DIB and how it was resolved through re-design of the DIB also is presented. This finding also provide the PCS designer the valuable information on the constraint of trace length and component layout one need to take into consideration when design a multi-site DIB use for high speed MCU testing to avoid AC or DC test failure induced by excessive capacitive loading and resistance drop over signal trace on the DIB.