{"title":"一个字可变的ROM","authors":"W. Spence, G. Lockwood, M. Shen, M. Trudel","doi":"10.1109/ISSCC.1977.1155709","DOIUrl":null,"url":null,"abstract":"A WORD ALTERABLE ROM (1024x4 P-channel nonvolatile memory) will be described. It can be used as a block erasable programmable ROM or as a word alterable RAM. Erase and write times are variable depending on the application and data retentivity required. A prime objective is microprocessor system compatibility. All address, data, control and clock lines are TTL compatible with pull-up resistors t o +5V. Input address, data and control lines are latched. Data outputs hold for the duration of the Chip Enable clock and then return to an open circuit condition for operation on a common data bus. Access time is 650 ns.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A word alterable ROM\",\"authors\":\"W. Spence, G. Lockwood, M. Shen, M. Trudel\",\"doi\":\"10.1109/ISSCC.1977.1155709\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A WORD ALTERABLE ROM (1024x4 P-channel nonvolatile memory) will be described. It can be used as a block erasable programmable ROM or as a word alterable RAM. Erase and write times are variable depending on the application and data retentivity required. A prime objective is microprocessor system compatibility. All address, data, control and clock lines are TTL compatible with pull-up resistors t o +5V. Input address, data and control lines are latched. Data outputs hold for the duration of the Chip Enable clock and then return to an open circuit condition for operation on a common data bus. Access time is 650 ns.\",\"PeriodicalId\":416313,\"journal\":{\"name\":\"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1977.1155709\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1977.1155709","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A WORD ALTERABLE ROM (1024x4 P-channel nonvolatile memory) will be described. It can be used as a block erasable programmable ROM or as a word alterable RAM. Erase and write times are variable depending on the application and data retentivity required. A prime objective is microprocessor system compatibility. All address, data, control and clock lines are TTL compatible with pull-up resistors t o +5V. Input address, data and control lines are latched. Data outputs hold for the duration of the Chip Enable clock and then return to an open circuit condition for operation on a common data bus. Access time is 650 ns.
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