一种0.7-2.5GHz NB-loT/GNSS/BLE混合锁相环,具有PA拉减和带外相位降噪功能

Jiahao Zhao, Xuansheng Ji, Su Han, Ziwei Wang, W. Rhee, Zhihua Wang
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摘要

采用28nm CMOS实现了一个0.7-2.5GHz带单D/VCO的NB-IoT/GNSS/BLE混合锁相环。通过仔细的频率规划,通过使用多模分频器链来减轻PA拉效应。2.5分频器放宽了D/VCO的调谐范围要求,减轻了NB-IoT HB频段的PA拉,而NB-IoT LB则设计了6分频器。采用8分频FIR滤波方法,设计了宽带分数n锁相环,而不会增加带外相位噪声。所提出的锁相环在0.9V电源下最大功耗为4.7mW。实验结果表明,该锁相环满足NB-IoT/GNSS/BLE标准的相位噪声和杂散要求。
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A 0.7-2.5GHz NB-loT/GNSS/BLE Hybrid PLL with PA Pulling Mitigation and Out-of-Band Phase Noise Reduction
A 0.7-2.5GHz NB-IoT/GNSS/BLE hybrid PLL with a single D/VCO is implemented in 28nm CMOS. With careful frequency planning, the PA pulling effect is mitigated by using a multi-mode divider chain. A divider-by-2.5 relaxes the tuning range requirement of the D/VCO and mitigates the PA pulling for NB-IoT HB band, while a divider-by-6 is designed for NB-IoT LB. With an 8-tap FIR filtering method, a wideband fractional-N PLL is designed without increasing the out-of-band phase noise. The proposed PLL consumes the maximum 4.7mW with 0.9V supply. Experimental results show that the PLL meets the phase noise and spur requirements of the NB-IoT/GNSS/BLE standards.
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