Interface and gate line edge roughness effects on intra die variance in mos device characteristics

Random fluctuations in fabrication process outcomes such as Si-SiO2 interface surface roughness (SR) and gate line edge roughness (LER) give rise to corresponding fluctuations in scaled down MOS device characteristics. These fluctuations are intra-die and inherent even to ideal processes. As such, they represent fiudamental limitations to the die-level uniformity of the properties of otherwise identical devices. Modeling based on statistical characterization of fluctuations in the characteristics of small 3D devices is becoming increasingly important to understand the implications for product designers and process engineers. [1-5] Presently, TCAD numerical simulation is the only tool available for investigating the complex interaction of these issues. In this work, we employ a novel device modeling approach based on thennodynamics and on variational mathematical methods. [6] We obtain closed-form expressions for threshold voltage (Vth), and device capacitance (C) at Onset of Strong Inversion (OSI) for MOS devices in the deep sub-0.1 micron regime. In our model SR is assumed to affect only the gate area whereas LER affects only the gate perimeter of the device. Figure 1 shows the SEM of the fabricated line used in our analysis of SR and LER. [7-8] We take the roughness of this line to be representative and characterize it by Fourier transforming the digitized data. By choosing a pdf to represent the entire spectrm we can then identify the average frequency and the variance. Figure 2 shows the FFT of the digitized data (circles) from Fig. 1, together with the lognormal pdf (solid line) used to fit the data. We have looked in some detail at three possible candidate pdfs: exponential, gaussian, and lognormal. For a combination of reasons we prefer the lognormal. [9] Our variational model predicts that the random deviation of threshold voltage due to LER should increase as the square of the roughness amplitude. Figure 3 shows this variation for a MOSCAP of gate length 35 nm and a width of 50 nm. Our results are compared here with results from Kim et al. [10] In both cases the variation appears to be quadratic in roughness amplitude. Figure 4 shows our prediction of the random deviation of total capacitance of the device at OSI for both LER and SR against standard deviation of roughness wavenumber. Figure 5 shows the random deviation of Vt for LER and SR against average roughness wavenumber according to our model. These statistical characteristics are extremely difficult to capture using TCAD. In contrast, the novelty and strong advantage of our modeling approach is that it allows us to treat the situation with less difficulty by explicitly incorporating these statistical quantities. Oxide thickness is one of the key parameters that affect the variance in Vh. Figure 6 shows the effect of variation in the oxide thickness on the random deviation of Vh according to our model. The model predicts that the deviation is greater for LER than for SR. Interestingly, the deviation in Vh due to roughness reduces drastically for oxide thicknesses less than 4 nm.