Clock Gating Efficiency and Impact on Power Optimization During Synthesis Flow

Nowadays, power optimization has become an important factor in VLSI design and various low power optimization techniques are being developed. Clock-Gating is considered one of the widely used techniques in VLSI power optimization. Gating the Clock path results in saving power by reducing wasted capacitances switching due to unnecessary activity in logic module paths, thus resulting in more wasted Switching power. Clock gating is not always beneficial, it presents some pitfalls and fallacies within its implementation in various VLSI designs, as well as it doesn't suit all kinds of VLSI logic circuits. In this paper, we measure the impact of the Clock-Gating technique on power as well as on design's performance. We have performed two separate trials, using 112 industrial designs from different technologies, the former trial enables Clock Gate insertion, and the latter does not insert Clock Gate cells in the design's circuitry. We intend to measure the impact of Clock Gating on power by measuring the Power variation and comparing metrics such Instance number Buffer & Inverter, Combinational blocks as well as QoR metrics such Runtime, wire-length, TNS, and Area. Results of this experiment showed that design circuits having Memories (SRAM, DFF, FIFO…) as dominant RTL modules, have the most impact on power when CG cells are inserted. Vice-versa power is less impacted by CG cells insertion for designs that contain microprocessors and Datapath blocks as dominant RTL instances.