A display-optimized processor

Details are given on the architectural design of a computer currently under construction which has been optimized for display processing and display generation. The design takes full advantage of evolving trends in ECL medium and large scale integrated circuits. The processor incorporates the concept of instruction set partitioning. Hardwired instructions are used for critical display requirements while general purpose flexibility is provided by externally microprogrammable asynchronous processors. Design cycle time for this 32 bit processor is under 100 nanoseconds for instruction fetch and execute. Processor hardware costs are under $25,000. The device is designed to generate a full color TV image of 512 by 512 resolution in 0.1 to 0.8 seconds for 3D images of up to 1000 polygon complexity with all hidden parts removed by software for hidden surface calculations. Due to its inherent generality the CPU may be expanded to encompass a wide variety of other specialized or real-time tasks with minor additional hardware.