60 GHz低噪声放大器与1千伏CDM保护在40纳米LP CMOS

2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems Pub Date : 2012-03-01 DOI:10.1109/SIRF.2012.6160126

K. Raczkowski, S. Thijs, J. Tseng, T. Chang, Ming-Hsiang Song, D. Linten, B. Nauwelaers, P. Wambacq

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引用次数: 4

摘要

本文介绍了一套采用40nm低功耗CMOS设计的微型三级60ghz LNAs。这些设计证明了基于电感的ESD保护方案在毫米波电路中的有效性和易用性。测量的ESD保护水平达到4.5 kV HBM, VFTLP测试高达7.6 A，并达到1 kV CDM的记录。同时，在1.1 V电源下，60 GHz时lna的NF小于8 dB，增益大于15 dB。这些电路可以有效地用作相控阵接收机的输入级。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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60 GHz low noise amplifiers with 1 kV CDM protection in 40 nm LP CMOS

This paper describes a set of miniature, three-stage 60 GHz LNAs designed in 40 nm LP CMOS. The designs prove effectiveness and ease of use of inductor-based ESD protection schemes applied to mm-wave circuits. The measured ESD protection levels reach 4.5 kV HBM, up to 7.6 A for VFTLP tests and a record of 1 kV CDM. At the same time, the NF of the LNAs is below 8 dB and the gain above 15 dB at 60 GHz, all at 1.1 V supply. These circuits can effectively be used as input stages of a phased array receiver.

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2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

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