双k间隔FinFET的寄生电容

2016 Conference on Emerging Devices and Smart Systems (ICEDSS) Pub Date : 2016-03-04 DOI:10.1109/ICEDSS.2016.7587783

Shilpa Bisnoi, S. Dasgupta

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引用次数: 0

摘要

本文研究了栅极搭接长度和高k间隔宽度对纳米级双k间隔FinFET寄生电容的影响。研究发现，最佳栅极搭接长度可以显著减小寄生电容。此外，还讨论了突变型掺杂对器件寄生电容的影响。所有的二维仿真均在二维Sentaurus TCAD设备模拟器上进行。

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Parasitic capacitances of Dual-K spacer FinFET

This paper presents the impact of gate underlap length and high-k spacer width on the parasitic capacitances of nanoscale Dual-K spacer FinFET. It was found that the optimum gate underlap length can considerably reduce the parasitic capacitances. Also, the impact of abrupt doping profile on the parasitic capacitance of the device is discussed. All the 2-D simulations were performed on 2-D Sentaurus TCAD device simulator.

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2016 Conference on Emerging Devices and Smart Systems (ICEDSS)

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