{"title":"平面图设计与优化的分析方法","authors":"S. Sutanthavibul, E. Shragowitz, J. B. Rosen","doi":"10.1109/DAC.1990.114852","DOIUrl":null,"url":null,"abstract":"An analytical method for VLSI general floorplan design and optimization is proposed. This method is based on a mixed integer programming model and all application of a standard mathematical software. The method allows arbitrary combinations of rigid and flexible modules. Various objective functions, such as chip area, interconnection length, timing delays or any combinations of them, are permitted. Routing space is estimated by the global router. Experimental data are provided.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"94","resultStr":"{\"title\":\"An analytical approach to floorplan design and optimization\",\"authors\":\"S. Sutanthavibul, E. Shragowitz, J. B. Rosen\",\"doi\":\"10.1109/DAC.1990.114852\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An analytical method for VLSI general floorplan design and optimization is proposed. This method is based on a mixed integer programming model and all application of a standard mathematical software. The method allows arbitrary combinations of rigid and flexible modules. Various objective functions, such as chip area, interconnection length, timing delays or any combinations of them, are permitted. Routing space is estimated by the global router. Experimental data are provided.<<ETX>>\",\"PeriodicalId\":118552,\"journal\":{\"name\":\"27th ACM/IEEE Design Automation Conference\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-06-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"94\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"27th ACM/IEEE Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DAC.1990.114852\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"27th ACM/IEEE Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DAC.1990.114852","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An analytical approach to floorplan design and optimization
An analytical method for VLSI general floorplan design and optimization is proposed. This method is based on a mixed integer programming model and all application of a standard mathematical software. The method allows arbitrary combinations of rigid and flexible modules. Various objective functions, such as chip area, interconnection length, timing delays or any combinations of them, are permitted. Routing space is estimated by the global router. Experimental data are provided.<>
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