{"title":"设计混淆教程:从晶体管到系统","authors":"S. Pagliarini","doi":"10.1109/LATS53581.2021.9651741","DOIUrl":null,"url":null,"abstract":"The recent advances in the area of design obfuscation are encouraging, but may present themselves as hard to read for a non-specialist audience. This tutorial uncovers these advances in a clear language, contrasting the approaches that can be implemented at layout level, in the netlist of a circuit, or even at chip level. This tutorial also highlights the available support, both from the tooling side and the logistics of fabricating an obfuscated integrated circuit.","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Tutorial on Design Obfuscation: from Transistors to Systems\",\"authors\":\"S. Pagliarini\",\"doi\":\"10.1109/LATS53581.2021.9651741\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The recent advances in the area of design obfuscation are encouraging, but may present themselves as hard to read for a non-specialist audience. This tutorial uncovers these advances in a clear language, contrasting the approaches that can be implemented at layout level, in the netlist of a circuit, or even at chip level. This tutorial also highlights the available support, both from the tooling side and the logistics of fabricating an obfuscated integrated circuit.\",\"PeriodicalId\":404536,\"journal\":{\"name\":\"2021 IEEE 22nd Latin American Test Symposium (LATS)\",\"volume\":\"82 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-08-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE 22nd Latin American Test Symposium (LATS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/LATS53581.2021.9651741\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 22nd Latin American Test Symposium (LATS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LATS53581.2021.9651741","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Tutorial on Design Obfuscation: from Transistors to Systems
The recent advances in the area of design obfuscation are encouraging, but may present themselves as hard to read for a non-specialist audience. This tutorial uncovers these advances in a clear language, contrasting the approaches that can be implemented at layout level, in the netlist of a circuit, or even at chip level. This tutorial also highlights the available support, both from the tooling side and the logistics of fabricating an obfuscated integrated circuit.