采用晶圆级底填料和低CTE环氧模复合材料的3D封装的可靠性

F. Cadacio, K. Rebibis, G. Capuz, R. Daily, C. Gerets, E. Sleeckx, F. Duval, T. Wang, R. A. Miller, G. Beyer, E. Beyne
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引用次数: 4

摘要

随着3D技术的出现来回答摩尔定律的挑战性限制,为了满足该技术的可靠性和稳健性,必须采用当今3D IC封装中的某些功能。用于TSV加工的屏障、μbump的冶金、用于堆叠的底料与集成电路组装材料的结合都对3D集成电路封装的可靠性和鲁棒性起着至关重要的作用。在这个3D封装中选择组装的材料之一是堆叠模具之间的底料。下填料为微凸起提供了机械稳定性,并在3D堆栈发送包装之前防止模具之间产生的间隙之间的水分。3D集成电路堆的下填充选择与使用毛细管下填充的行业标准有很大不同。目前3D设备的堆叠是通过热压工艺完成的,这与行业中通常采用的大规模回流芯片连接工艺有很大不同。这主要是由于3D ic的窄间隙和非常精细的凹凸间距。由于3D叠层的这些细小而狭窄的几何变化,将毛细管底填工艺与热压粘合工艺结合使用是相当困难的。使用预施加的下填料,如晶圆级下填料(wluf)和无流下填料(nuf),结合热压键合工艺,已被证明是3D堆叠的可行解决方案。在热压粘合中使用无流下填(NUF)也会引入加工复杂性(见图1.0)。其复杂性在于分配非常精确的体积来填充小于15um的间隙。,在大多数情况下,需要分配的底料量在亚毫克级别。分配这种数量的材料需要非常精确的喷射分配器,并且需要在喷射nuf方面进行大量的表征。利用晶圆级欠填充(WLUFs)消除了计算正确喷射参数以填充整个UF间隙的复杂性。但是,上述材料的几个方面需要考虑,例如其透明度(见图2.0)、厚度变化、存储/分期条件和熔体粘度,所有这些都在使材料可用于3D堆叠方面发挥重要作用。选择正确的模具复合材料用于3D封装也被认为是非常重要的可靠性方面的封装性能。在选择过程中,必须评估和量化模具化合物的CTE和翘曲行为(见图3.0)。本文将展示和讨论Wafer Level Underfill和low CTE模具复合材料的选择过程以及这些材料组合的封装可靠性。采用Jedec标准可靠性试验(MSL、TCT-B、HTS和PCT)量化三维封装的可靠性性能。在不同的可靠性读数期间,检查了测试车辆菊花链的电气测试和封装在封装接口分层方面的稳健性。
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Reliability of 3D package using wafer level underfill and low CTE epoxy mold compound materials
With the emergence of 3D technology to answer the challenging limits of Moore's Law, certain features in today's 3D IC packages have to be adopted in order to meet the reliability and robustness of this technology. The barriers used for TSV processing, the metallurgy of the μbump, the underfill material used in stacking in combination with the IC assembly materials all play a vital role in the reliability and robustness of a 3D IC package. One of the materials selected for assembly in this 3D package was the underfill between the stacked dies. The underfill provides the mechanical stability for micro-bumps and prevents moisture between the resulting gaps between dies before the 3D stack is sent for packaging. Underfilling options for 3D IC stacks differs significantly to what has been a standard in the industry which is in using capillary underfills. Stacking of the 3D device is currently done using a thermocompression process, which is quite different from the mass reflow chip attach process normally done in the industry. This is mainly due to the narrow gaps and very fine bump pitches of 3D ICs. As a result of these fine and narrow geometry change in 3D stacks, it is quite difficult to use the capillary underfill process in combination with the thermo-compression bonding process. The use of pre-applied underfills such as the Wafer Level Underfills (WLUFs) and No Flow Underfills (NUFs) in combination with the thermo-compression bonding process has shown to be a viable solution for 3D stacking. Using No-Flow Underfills (NUF) in thermo-compression bonding also introduce processing complexities (see Figure 1.0). The complexity lies in dispensing a very accurate volume to fill a gap lower than 15um., in most cases, the amount of underfill material that needs to be dispense is in the submilligram level. Dispensing this amount of material requires very accurate jet dispensers and will need a lot of characterization in terms of jetting the NUFs. By using Wafer Level Underfills (WLUFs) takes out the complexity of figuring out the correct jetting parameters in order to fill the entire UF gap. But there are several aspects of the said material that needs to be taken into consideration such as its transparency (see Figure 2.0), thickness variations storage/staging conditions and melt viscosity all of which play important roles in making the material useable for 3D stacks. Selection of the correct mold compound to be used for the 3D package is also deemed very important in terms of the reliability performance of the package. The CTE and warpage behavior of the mold compound had to be evaluated and quantified in the selection process (see Figure 3.0). In this paper, the selection process of Wafer Level Underfill and low CTE mold compound materials and the resulting package reliability of the combination of these materials will be shown and discussed. Jedec standard reliability tests (MSL, TCT-B, HTS and PCT) were used in quantifying the reliability performance of the 3D package. Electrical tests on the daisy chain of the test vehicle and package robustness in terms delamination in the interfaces of the package were checked during the different reliability readouts.
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