{"title":"时序驱动的多fpga板分区","authors":"R. Burra, D. Bhatia","doi":"10.1109/ICVD.1998.646609","DOIUrl":null,"url":null,"abstract":"System level design is increasingly turning towards FPGAs to take advantage of their low cost and fast prototyping. In this paper we present a timing driven partitioning approach for an architecturally constrained multi-FPGA system. The partitioning approach uses path-based clustering based on the work by Dennis et al. (1995) and retiming. The board-level architecture is based on the PCB model consisting of four Xilinx 4013 FPGAs. The proposed algorithm has been tested on large scale real designs.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Timing driven multi-FPGA board partitioning\",\"authors\":\"R. Burra, D. Bhatia\",\"doi\":\"10.1109/ICVD.1998.646609\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"System level design is increasingly turning towards FPGAs to take advantage of their low cost and fast prototyping. In this paper we present a timing driven partitioning approach for an architecturally constrained multi-FPGA system. The partitioning approach uses path-based clustering based on the work by Dennis et al. (1995) and retiming. The board-level architecture is based on the PCB model consisting of four Xilinx 4013 FPGAs. The proposed algorithm has been tested on large scale real designs.\",\"PeriodicalId\":139023,\"journal\":{\"name\":\"Proceedings Eleventh International Conference on VLSI Design\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-01-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Eleventh International Conference on VLSI Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICVD.1998.646609\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Eleventh International Conference on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICVD.1998.646609","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
System level design is increasingly turning towards FPGAs to take advantage of their low cost and fast prototyping. In this paper we present a timing driven partitioning approach for an architecturally constrained multi-FPGA system. The partitioning approach uses path-based clustering based on the work by Dennis et al. (1995) and retiming. The board-level architecture is based on the PCB model consisting of four Xilinx 4013 FPGAs. The proposed algorithm has been tested on large scale real designs.
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