Current source model of combinational logic gates for accurate gate-level circuit analysis and timing analysis

Many current source models (CSMs) have been proposed for the gate-level circuit analysis and timing analysis for sub-90-nm CMOS designs during the past decade. However, most of them may suffer from large delay errors for multiple-stages of combinational logic gates. This paper presents an extended CSM which can provide high accuracy in both single-stage and multiple-stage combinational logic gates. The proposed CSM consists of voltage-controlled current source, input and output parasitic capacitances, Miller capacitance and calibration input capacitance parallel to the characterized input capacitance. The calibration input capacitance helps to model the input node more accurately. In experiments, the proposed CSM outperformed the benchmark CSMs in the average root-mean squared error (RMSE) and the average 50%-to-50% gate delay error.