{"title":"欧洲X-FEL的低电平射频系统架构","authors":"T. Jezynski, S. Simrock","doi":"10.1109/MIXDES.2006.1706544","DOIUrl":null,"url":null,"abstract":"The Low-Level Radio Frequency System (LLRF) for the superconducting cavities of the European X-FEL must provide exceptional stability of the accelerating RF field amplitude (0.01%) and phase (0.01 degrees) at a frequency of 1.3 GHz. These requirements must be achieved in pulsed operation mode with one klystron driving 32 cavities. It is thus necessary to design and build a modern LLRF control system, consisting of state of the art hardware and sophisticated control algorithms requiring high gain, low noise, fast and high resolution ADCs (up 16 bits, >100MHz), and high performance data processing using FPGAs and DSPs with low latency. A complete LLRF system must support more than 100 analogue input channels. This paper describes one possible architecture, which will be tested at DESY by the end of 2006.","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"The low level radio frequency system architecture for the european X-FEL\",\"authors\":\"T. Jezynski, S. Simrock\",\"doi\":\"10.1109/MIXDES.2006.1706544\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The Low-Level Radio Frequency System (LLRF) for the superconducting cavities of the European X-FEL must provide exceptional stability of the accelerating RF field amplitude (0.01%) and phase (0.01 degrees) at a frequency of 1.3 GHz. These requirements must be achieved in pulsed operation mode with one klystron driving 32 cavities. It is thus necessary to design and build a modern LLRF control system, consisting of state of the art hardware and sophisticated control algorithms requiring high gain, low noise, fast and high resolution ADCs (up 16 bits, >100MHz), and high performance data processing using FPGAs and DSPs with low latency. A complete LLRF system must support more than 100 analogue input channels. This paper describes one possible architecture, which will be tested at DESY by the end of 2006.\",\"PeriodicalId\":318768,\"journal\":{\"name\":\"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-06-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MIXDES.2006.1706544\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MIXDES.2006.1706544","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The low level radio frequency system architecture for the european X-FEL
The Low-Level Radio Frequency System (LLRF) for the superconducting cavities of the European X-FEL must provide exceptional stability of the accelerating RF field amplitude (0.01%) and phase (0.01 degrees) at a frequency of 1.3 GHz. These requirements must be achieved in pulsed operation mode with one klystron driving 32 cavities. It is thus necessary to design and build a modern LLRF control system, consisting of state of the art hardware and sophisticated control algorithms requiring high gain, low noise, fast and high resolution ADCs (up 16 bits, >100MHz), and high performance data processing using FPGAs and DSPs with low latency. A complete LLRF system must support more than 100 analogue input channels. This paper describes one possible architecture, which will be tested at DESY by the end of 2006.