{"title":"基于本地模拟的数据流缓存预测","authors":"F. Wolf, R. Ernst","doi":"10.1109/HLDVT.2000.889577","DOIUrl":null,"url":null,"abstract":"Accurate cache modeling and analysis are crucial to formally determine program execution time. Current cache analysis techniques combine basic block level cache modeling with explicit or implicit program path analysis. We show how to extend program and data cache modeling from basic blocks to program segments thereby increasing the overall execution time analysis precision. The approach combines architecture simulation, data flow analysis and implicit path enumeration.","PeriodicalId":113229,"journal":{"name":"Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"Data flow based cache prediction using local simulation\",\"authors\":\"F. Wolf, R. Ernst\",\"doi\":\"10.1109/HLDVT.2000.889577\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Accurate cache modeling and analysis are crucial to formally determine program execution time. Current cache analysis techniques combine basic block level cache modeling with explicit or implicit program path analysis. We show how to extend program and data cache modeling from basic blocks to program segments thereby increasing the overall execution time analysis precision. The approach combines architecture simulation, data flow analysis and implicit path enumeration.\",\"PeriodicalId\":113229,\"journal\":{\"name\":\"Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)\",\"volume\":\"47 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-11-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HLDVT.2000.889577\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HLDVT.2000.889577","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Data flow based cache prediction using local simulation
Accurate cache modeling and analysis are crucial to formally determine program execution time. Current cache analysis techniques combine basic block level cache modeling with explicit or implicit program path analysis. We show how to extend program and data cache modeling from basic blocks to program segments thereby increasing the overall execution time analysis precision. The approach combines architecture simulation, data flow analysis and implicit path enumeration.