石墨烯纳米带肖特基势垒场效应管:挑战与机遇

Q. Zhang, Y. Lu, G. Xing, C. Richter, S. Koester, S. Koswatta
{"title":"石墨烯纳米带肖特基势垒场效应管:挑战与机遇","authors":"Q. Zhang, Y. Lu, G. Xing, C. Richter, S. Koester, S. Koswatta","doi":"10.1109/DRC.2010.5551933","DOIUrl":null,"url":null,"abstract":"On the ITRS roadmap [1], the physical gate length, LG, has been rapidly scaling down, and will reach values below ∼ 10nm beyond 2020 (see Table I, shaded region). The single-gate (SG) extremely thin SOI (ETSOI) MOSFET, the double-gate (DG) FinFET, and the gate-all-around (GAA) Si nanowire (SiNW) MOSFET geometries may facilitate such scaling [2–4]. Nevertheless, sub-10nm LG scaling will be a great challenge because of the significant mobility degradation [5] and channel thickness variations [2] in the aforementioned geometries with a few-nanometer body thicknesses as required by electrostatic short-channel considerations. Therefore, new device geometries and technologies are required that could simultaneously maintain the electrostatic integrity and the superior transport properties for sub-10nm LG scaling. It has been recently shown that the atomic-thin- body (ATB) geometry can meet the electrostatic requirements for LG ≤ 10nm [6]. At the ATB limit, carbon electronics based on graphene nanoribbons (GNRs) with tunable band gaps [7] have been widely considered for high-performance digital electronics [8–10]. Here, ballistic transport of GNR Schottky-barrier (SB) FETs is simulated self-consistently [6], including both thermionic emission and tunneling. We show the better gate length scalability of GNRs compared to Si MOSFETs, even though significant material related challenges will have to be overcome. LG scaling below 10nm is mainly limited by direct source-to-drain tunneling and the ambipolar effect in the off-state, which can be suppressed by narrower ribbon widths (of the order ∼ 1nm), and larger effective masses obtained from bandstructure engineering. If a negative metal-graphene SB-height could be achieved, the GNR SB-FET could operate without significant series resistance effects, and deliver high on-current (ION ) [11]. The performance of the ultimate GNR SB-FETs is comparable to the MOSFET targets of the ITRS roadmap [1].","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Graphene nanoribbon Schottky-barrier FETs for end-of-the-roadmap CMOS: Challenges and opportunities\",\"authors\":\"Q. Zhang, Y. Lu, G. Xing, C. Richter, S. Koester, S. Koswatta\",\"doi\":\"10.1109/DRC.2010.5551933\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"On the ITRS roadmap [1], the physical gate length, LG, has been rapidly scaling down, and will reach values below ∼ 10nm beyond 2020 (see Table I, shaded region). The single-gate (SG) extremely thin SOI (ETSOI) MOSFET, the double-gate (DG) FinFET, and the gate-all-around (GAA) Si nanowire (SiNW) MOSFET geometries may facilitate such scaling [2–4]. Nevertheless, sub-10nm LG scaling will be a great challenge because of the significant mobility degradation [5] and channel thickness variations [2] in the aforementioned geometries with a few-nanometer body thicknesses as required by electrostatic short-channel considerations. Therefore, new device geometries and technologies are required that could simultaneously maintain the electrostatic integrity and the superior transport properties for sub-10nm LG scaling. It has been recently shown that the atomic-thin- body (ATB) geometry can meet the electrostatic requirements for LG ≤ 10nm [6]. At the ATB limit, carbon electronics based on graphene nanoribbons (GNRs) with tunable band gaps [7] have been widely considered for high-performance digital electronics [8–10]. Here, ballistic transport of GNR Schottky-barrier (SB) FETs is simulated self-consistently [6], including both thermionic emission and tunneling. We show the better gate length scalability of GNRs compared to Si MOSFETs, even though significant material related challenges will have to be overcome. LG scaling below 10nm is mainly limited by direct source-to-drain tunneling and the ambipolar effect in the off-state, which can be suppressed by narrower ribbon widths (of the order ∼ 1nm), and larger effective masses obtained from bandstructure engineering. If a negative metal-graphene SB-height could be achieved, the GNR SB-FET could operate without significant series resistance effects, and deliver high on-current (ION ) [11]. The performance of the ultimate GNR SB-FETs is comparable to the MOSFET targets of the ITRS roadmap [1].\",\"PeriodicalId\":396875,\"journal\":{\"name\":\"68th Device Research Conference\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-06-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"68th Device Research Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DRC.2010.5551933\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"68th Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2010.5551933","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

摘要

在ITRS路线图[1]中,物理栅极长度LG已经迅速缩小,并将在2020年之后达到低于~ 10nm的值(见表1,阴影区域)。单门(SG)极薄SOI (ETSOI) MOSFET,双门(DG) FinFET和栅极全能(GAA) Si纳米线(SiNW) MOSFET的几何形状可能有助于这种缩放[2-4]。然而,低于10nm的LG缩放将是一个巨大的挑战,因为上述几何形状中显著的迁移率下降[5]和通道厚度变化[2],由于静电短通道考虑所需的几纳米体厚度。因此,需要新的器件几何形状和技术,以同时保持10纳米以下LG缩放的静电完整性和优越的输运特性。最近有研究表明,原子薄体(ATB)几何结构可以满足LG≤10nm的静电要求[6]。在ATB极限下,基于具有可调谐带隙的石墨烯纳米带(gnr)的碳电子器件[7]已被广泛考虑用于高性能数字电子器件[8-10]。本文自一致地模拟了GNR肖特基势垒(SB)场效应管的弹道输运[6],包括热离子发射和隧穿。我们展示了与Si mosfet相比,gnr具有更好的栅极长度可扩展性,尽管必须克服重大的材料相关挑战。10nm以下的LG缩放主要受到直接源-漏极隧道效应和关闭状态下的双极性效应的限制,这可以通过更窄的能带宽度(约1nm)和更大的有效质量来抑制。如果可以实现负的金属-石墨烯SB-height,则GNR SB-FET可以在没有明显串联电阻效应的情况下工作,并提供高导通电流(ION)[11]。最终GNR sb - fet的性能可与ITRS路线图的MOSFET目标相媲美[1]。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Graphene nanoribbon Schottky-barrier FETs for end-of-the-roadmap CMOS: Challenges and opportunities
On the ITRS roadmap [1], the physical gate length, LG, has been rapidly scaling down, and will reach values below ∼ 10nm beyond 2020 (see Table I, shaded region). The single-gate (SG) extremely thin SOI (ETSOI) MOSFET, the double-gate (DG) FinFET, and the gate-all-around (GAA) Si nanowire (SiNW) MOSFET geometries may facilitate such scaling [2–4]. Nevertheless, sub-10nm LG scaling will be a great challenge because of the significant mobility degradation [5] and channel thickness variations [2] in the aforementioned geometries with a few-nanometer body thicknesses as required by electrostatic short-channel considerations. Therefore, new device geometries and technologies are required that could simultaneously maintain the electrostatic integrity and the superior transport properties for sub-10nm LG scaling. It has been recently shown that the atomic-thin- body (ATB) geometry can meet the electrostatic requirements for LG ≤ 10nm [6]. At the ATB limit, carbon electronics based on graphene nanoribbons (GNRs) with tunable band gaps [7] have been widely considered for high-performance digital electronics [8–10]. Here, ballistic transport of GNR Schottky-barrier (SB) FETs is simulated self-consistently [6], including both thermionic emission and tunneling. We show the better gate length scalability of GNRs compared to Si MOSFETs, even though significant material related challenges will have to be overcome. LG scaling below 10nm is mainly limited by direct source-to-drain tunneling and the ambipolar effect in the off-state, which can be suppressed by narrower ribbon widths (of the order ∼ 1nm), and larger effective masses obtained from bandstructure engineering. If a negative metal-graphene SB-height could be achieved, the GNR SB-FET could operate without significant series resistance effects, and deliver high on-current (ION ) [11]. The performance of the ultimate GNR SB-FETs is comparable to the MOSFET targets of the ITRS roadmap [1].
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Recent progress in GaN FETs on silicon substrate for switching and RF power applications Room temperature nonlinear ballistic nanodevices for logic applications III–V FET channel designs for high current densities and thin inversion layers High retention-time nonvolatile amorphous silicon TFT memory for static active matrix OLED display without pixel refresh Non-volatile spin-transfer torque RAM (STT-RAM)
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1