Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551987
J. Verma, J. Simon, V. Protasenko, G. Xing, D. Jena
III–V nitride semiconductors are direct band gap semiconductors spanning a wide range of band gaps from 0.7 eV (InN, IR), through 3.4 eV (GaN, UV) to 6.2 eV (AlN, deep UV). This makes them uniquely suited for fabricating visible and UV LEDs [1]. UV LEDs have applications in water purification, microscopy and chemical analysis. However, wide band gap nitrides suffer from poor p-type doping owing to large activation energy of Mg acceptor dopant ( EA∼200 meV for GaN [2] and 650 meV for AlN [3]). This results in low thermal activation of holes at room temperature and causes low p-type conductivity. III–V nitrides also exhibit large built-in polarization field with spontaneous and strain induced piezoelectric components [4]. The polarization has recently been exploited to demonstrate N-face AlGaN/GaN p-n heterojunctions with improved p-type conductivities and electroluminescence [5]. In this work, we demonstrate that incorporating quantum wells (QWs) into the active regions improves electroluminescence (EL). Simultaneously, a number of advantages of N-face structures emerge from the point of view of polarization-engineering.
III-V型氮化物半导体是直接带隙半导体，其带隙范围从0.7 eV (InN, IR)到3.4 eV (GaN, UV)到6.2 eV (AlN，深UV)。这使得它们非常适合制造可见光和紫外led[1]。UV led在水净化，显微镜和化学分析方面有应用。然而，由于Mg受体掺杂的活化能较大(GaN[2]为EA ~ 200 meV, AlN[3]为650 meV)，宽带隙氮化物的p型掺杂效果较差。这导致孔在室温下的低热活化，并导致低p型电导率。III-V型氮化物也表现出较大的内置极化场，具有自发和应变诱导的压电元件[4]。最近，该极化被用来证明n面AlGaN/GaN p-n异质结具有改进的p型电导率和电致发光[5]。在这项工作中，我们证明了将量子阱(QWs)纳入有源区域可以改善电致发光(EL)。同时，从偏振工程的角度来看，n面结构具有许多优点。
{"title":"Polarization-engineered N-face III–V nitride quantum well LEDs","authors":"J. Verma, J. Simon, V. Protasenko, G. Xing, D. Jena","doi":"10.1109/DRC.2010.5551987","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551987","url":null,"abstract":"III–V nitride semiconductors are direct band gap semiconductors spanning a wide range of band gaps from 0.7 eV (InN, IR), through 3.4 eV (GaN, UV) to 6.2 eV (AlN, deep UV). This makes them uniquely suited for fabricating visible and UV LEDs [1]. UV LEDs have applications in water purification, microscopy and chemical analysis. However, wide band gap nitrides suffer from poor p-type doping owing to large activation energy of Mg acceptor dopant ( EA∼200 meV for GaN [2] and 650 meV for AlN [3]). This results in low thermal activation of holes at room temperature and causes low p-type conductivity. III–V nitrides also exhibit large built-in polarization field with spontaneous and strain induced piezoelectric components [4]. The polarization has recently been exploited to demonstrate N-face AlGaN/GaN p-n heterojunctions with improved p-type conductivities and electroluminescence [5]. In this work, we demonstrate that incorporating quantum wells (QWs) into the active regions improves electroluminescence (EL). Simultaneously, a number of advantages of N-face structures emerge from the point of view of polarization-engineering.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127368554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551962
A. Vallett, S. Minassian, S. Datta, J. Redwing, T. Mayer
Recent interest in low-power electronics has sparked considerable interested in gate-controlled tunneling-based transistors (TFETs), which have demonstrated inverse subthreshold slopes (S) better than the MOSFET limit of 60 mV/dec.1 While the natural progression of these devices to nanoscale dimensions promises improved performance23, there is a lack of experimental data regarding the physics of tunneling at reduced dimensions. Here we present a TFET fabricated from an individual axially-doped p+-n-n+ Si nanowire in a device layout that enables the study of tunneling physics as the wire dimensions are scaled to the 1D transport regime.
{"title":"Fabrication of axially-doped silicon nanowire tunnel FETs and characterization of tunneling current","authors":"A. Vallett, S. Minassian, S. Datta, J. Redwing, T. Mayer","doi":"10.1109/DRC.2010.5551962","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551962","url":null,"abstract":"Recent interest in low-power electronics has sparked considerable interested in gate-controlled tunneling-based transistors (TFETs), which have demonstrated inverse subthreshold slopes (S) better than the MOSFET limit of 60 mV/dec.1 While the natural progression of these devices to nanoscale dimensions promises improved performance23, there is a lack of experimental data regarding the physics of tunneling at reduced dimensions. Here we present a TFET fabricated from an individual axially-doped p+-n-n+ Si nanowire in a device layout that enables the study of tunneling physics as the wire dimensions are scaled to the 1D transport regime.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128562414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551926
D. Wineland
In 1994, Peter Shor showed that a computer based on the rules that govern quantum systems could efficiently factorize large numbers. Because of the implications of this idea on the security of data encryption, funding for the development of such a device increased significantly and sparked research for other applications of quantum information processing (QIP). Since then, the elementary logic operations and simple algorithms for such a device have been demonstrated, but building a useful quantum computer is an extremely daunting task due to the necessity of overcoming decoherence of the inherent large entangled quantum superposition states. Nevertheless, in the near term, the principles of QIP are finding applications in metrology (such as for atomic clocks) and may also provide a way to efficiently simulate other quantum systems of interest, a motivation that intrigued Richard Feynman in the early 1980's. A number of physical systems are currently considered for building a quantum computer; this talk will focus on the use of registers of atomic ions, but connections to other possible physical implementations are rather direct.
{"title":"Computation with quantum systems","authors":"D. Wineland","doi":"10.1109/DRC.2010.5551926","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551926","url":null,"abstract":"In 1994, Peter Shor showed that a computer based on the rules that govern quantum systems could efficiently factorize large numbers. Because of the implications of this idea on the security of data encryption, funding for the development of such a device increased significantly and sparked research for other applications of quantum information processing (QIP). Since then, the elementary logic operations and simple algorithms for such a device have been demonstrated, but building a useful quantum computer is an extremely daunting task due to the necessity of overcoming decoherence of the inherent large entangled quantum superposition states. Nevertheless, in the near term, the principles of QIP are finding applications in metrology (such as for atomic clocks) and may also provide a way to efficiently simulate other quantum systems of interest, a motivation that intrigued Richard Feynman in the early 1980's. A number of physical systems are currently considered for building a quantum computer; this talk will focus on the use of registers of atomic ions, but connections to other possible physical implementations are rather direct.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126787226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551976
D. Mourey, D. Zhao, Ho Him R. Fok, Yuanyuan Li, T. Jackson
Oxide semiconductor electronics may enable new applications including large-area, flexible, integrated systems. ZnO thin film transistors have been reported with field-effect mobility > 100 cm2/V·s, on-current density > 700 mA/mm, and microwave operation (fT > 2 GHz, fmax > 7 GHz) for ZnO deposited by pulsed laser deposition at 400°C.[1] Other oxide semiconductors, including amorphous and crystalline mixtures of I2O3, Ga2O3, ZnO, have also been widely studied, and high mobility (> 30 cm2/V·s) thin film transistors and circuits with propagation delays < 1 ns/stage have been reported.[2,3] However, most of these high performance demonstrations were done on single crystal semiconductor substrates with high thermal conductivity. Here we find that self-heating and not drain-induced barrier lowering as previously reported [1] is the physical mechanism responsible for the output conductance (gd = dIDS/dVDS) observed in a range of oxide thin film transistors. In particular we find that self-heating is a significant limiting factor for the performance of oxide devices and circuits on low-cost, low-thermal conductivity substrates such as glass and plastic.
{"title":"Thermal effects in oxide TfTs","authors":"D. Mourey, D. Zhao, Ho Him R. Fok, Yuanyuan Li, T. Jackson","doi":"10.1109/DRC.2010.5551976","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551976","url":null,"abstract":"Oxide semiconductor electronics may enable new applications including large-area, flexible, integrated systems. ZnO thin film transistors have been reported with field-effect mobility > 100 cm<sup>2</sup>/V·s, on-current density > 700 mA/mm, and microwave operation (f<inf>T</inf> > 2 GHz, f<inf>max</inf> > 7 GHz) for ZnO deposited by pulsed laser deposition at 400°C.[1] Other oxide semiconductors, including amorphous and crystalline mixtures of I<inf>2</inf>O<inf>3</inf>, Ga<inf>2</inf>O<inf>3</inf>, ZnO, have also been widely studied, and high mobility (> 30 cm<sup>2</sup>/V·s) thin film transistors and circuits with propagation delays < 1 ns/stage have been reported.[2,3] However, most of these high performance demonstrations were done on single crystal semiconductor substrates with high thermal conductivity. Here we find that self-heating and not drain-induced barrier lowering as previously reported [1] is the physical mechanism responsible for the output conductance (g<inf>d</inf> = dI<inf>DS</inf>/dV<inf>DS</inf>) observed in a range of oxide thin film transistors. In particular we find that self-heating is a significant limiting factor for the performance of oxide devices and circuits on low-cost, low-thermal conductivity substrates such as glass and plastic.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129081095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551931
K. Lam, H. Da, S. Chin, G. Samudra, Y. Yeo, G. Liang
Novel device structures and electronic materials are required to further enhance the performance of digital circuits after the current MOSFET technology reaches its physical limits. While tunneling mechanism degrades the short channel MOSFET performance, it can be utilized as the major device operation in tunneling field-effect transistors (TFET) with promising features such as lower sub-threshold swing and OFF-state current (IOFF). Furthermore, semiconducting graphene nanoribbon (GNR) has been proposed as a potential electronic material for TFET application due to its unique properties such as ultra-thin body structure and high carrier mobility. A small bandgap (EG) material near the source-channel interface can be introduced to form heterojunction (HJ) which leads to a larger ION [1–3]. Therefore, in this work, we investigate the impact of the length and EG of this HJ region on the device performance of graphene nanoribbon TFET.
{"title":"A computational study on the device performance of graphene nanoribbon heterojunction tunneling FETs based on bandgap engineering","authors":"K. Lam, H. Da, S. Chin, G. Samudra, Y. Yeo, G. Liang","doi":"10.1109/DRC.2010.5551931","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551931","url":null,"abstract":"Novel device structures and electronic materials are required to further enhance the performance of digital circuits after the current MOSFET technology reaches its physical limits. While tunneling mechanism degrades the short channel MOSFET performance, it can be utilized as the major device operation in tunneling field-effect transistors (TFET) with promising features such as lower sub-threshold swing and OFF-state current (IOFF). Furthermore, semiconducting graphene nanoribbon (GNR) has been proposed as a potential electronic material for TFET application due to its unique properties such as ultra-thin body structure and high carrier mobility. A small bandgap (EG) material near the source-channel interface can be introduced to form heterojunction (HJ) which leads to a larger ION [1–3]. Therefore, in this work, we investigate the impact of the length and EG of this HJ region on the device performance of graphene nanoribbon TFET.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121526063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551855
N. Mojumder, C. Augustine, D. Nikonov, K. Roy
We investigate electronic transport and magnetization dynamics associated with current induced spin-torque effects in dual barrier magnetic tunnel junctions using Non-Equilibrium Green's Function formalism and Landau-Lifshitz- Gilbert (LLG) equation self-consistently. In a dual barrier penta-layer MTJ, a set of geometry and band-structure parameters including the free-layer thickness, oxide barrier height, width of the tunneling barrier and applied voltage jointly determines the position of resonant peaks and valleys within the energy range of interest. The combined effect of these design parameters to enhance the in-plane and out-of-plane spin-torque efficiencies in both aligned and anti-aligned penta-layer MTJs [Fig. 1] has been studied comprehensively. We quantify the impact of non-monotonic quantum well states for majority and minority spin electrons inside the thin free layer on the spin-torque effects in penta-layer MTJs. We essentially explore the design space for both the aligned and anti-aligned penta-layer MTJs optimized for read/write stabilities, improved TMR and low power. The crucial role of anti-aligned penta-layer MTJs in reducing the Energy-Delay-Product (EDP) during write over tri-layer MTJs has also been reported quantitatively.
{"title":"Spin torques estimation and magnetization dynamics in dual barrier resonant tunneling penta-layer magnetic tunnel junctions","authors":"N. Mojumder, C. Augustine, D. Nikonov, K. Roy","doi":"10.1109/DRC.2010.5551855","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551855","url":null,"abstract":"We investigate electronic transport and magnetization dynamics associated with current induced spin-torque effects in dual barrier magnetic tunnel junctions using Non-Equilibrium Green's Function formalism and Landau-Lifshitz- Gilbert (LLG) equation self-consistently. In a dual barrier penta-layer MTJ, a set of geometry and band-structure parameters including the free-layer thickness, oxide barrier height, width of the tunneling barrier and applied voltage jointly determines the position of resonant peaks and valleys within the energy range of interest. The combined effect of these design parameters to enhance the in-plane and out-of-plane spin-torque efficiencies in both aligned and anti-aligned penta-layer MTJs [Fig. 1] has been studied comprehensively. We quantify the impact of non-monotonic quantum well states for majority and minority spin electrons inside the thin free layer on the spin-torque effects in penta-layer MTJs. We essentially explore the design space for both the aligned and anti-aligned penta-layer MTJs optimized for read/write stabilities, improved TMR and low power. The crucial role of anti-aligned penta-layer MTJs in reducing the Energy-Delay-Product (EDP) during write over tri-layer MTJs has also been reported quantitatively.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"184 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134024675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551938
H. Zhao, N. Goel, J. Huang, Y. Chen, J. Yum, Y. Wang, F. Zhou, F. Xue, J. Lee
We demonstrate key factors enabling mobility improvement at both low charge density and high density (>5×1012/cm2) in In0.7Ga0.3As quantum-well MOSFETs. We further show sub-threshold swing (SS) and on-current (Id) improvement in tunneling FETs (TFETs). By reducing EOT, optimizing the top-barrier/high-к interface, and confining carriers in In0.7Ga0.3As channel using In0.52Al0.48As bottom-barrier, SS and mobility of MOSFETs were improved from 152 to 99 mV/dec and from ∼2500 to ∼5000 cm2/V-s, respectively. TFETs achieved small SS (96 mV/dec) and high Id (55 µA/µm) due to low EOT and abrupt, vertical insitu grown III–V epitaxial junctions.
{"title":"Factors enhancing In0.7Ga0.3As MOSFETs and tunneling FETs device performance","authors":"H. Zhao, N. Goel, J. Huang, Y. Chen, J. Yum, Y. Wang, F. Zhou, F. Xue, J. Lee","doi":"10.1109/DRC.2010.5551938","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551938","url":null,"abstract":"We demonstrate key factors enabling mobility improvement at both low charge density and high density (>5×10<sup>12</sup>/cm<sup>2</sup>) in In<inf>0.7</inf>Ga<inf>0.3</inf>As quantum-well MOSFETs. We further show sub-threshold swing (SS) and on-current (I<inf>d</inf>) improvement in tunneling FETs (TFETs). By reducing EOT, optimizing the top-barrier/high-к interface, and confining carriers in In<inf>0.7</inf>Ga<inf>0.3</inf>As channel using In<inf>0.52</inf>Al<inf>0.48</inf>As bottom-barrier, SS and mobility of MOSFETs were improved from 152 to 99 mV/dec and from ∼2500 to ∼5000 cm<sup>2</sup>/V-s, respectively. TFETs achieved small SS (96 mV/dec) and high I<inf>d</inf> (55 µA/µm) due to low EOT and abrupt, vertical insitu grown III–V epitaxial junctions.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"203 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131404897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551975
E. Chen, D. Lottis, A. Driskill-Smith, D. Druist, V. Nikitin, S. Watts, Xueti Tang, D. Apalkov
Non-volatile STT-RAM (spin transfer torque random access memory) is a new memory technology that combines the capacity and cost benefits of DRAM, the fast read and write performance of SRAM and the non-volatility of Flash with essentially unlimited endurance. It has excellent write selectivity, excellent scalability beyond the 45 nm technology node, low power consumption, and a simpler architecture and manufacturing process than first-generation, field-switched MRAM. A magnetic tunnel junction (MTJ) device (Fig. 1) is used as the information storage memory element, and its magneto-resistance is used for information read-out. To make the STT-RAM technology competitive with mainstream semiconductor memories, the writing current has to be reduced so that the MTJ can be switched by a minimum sized CMOS transistor. In this paper, we discuss our approaches and results in writing current reduction; device read and write performances; robustness against read disturb switching and barrier break down; and prospects of scaling to future smaller nodes.
{"title":"Non-volatile spin-transfer torque RAM (STT-RAM)","authors":"E. Chen, D. Lottis, A. Driskill-Smith, D. Druist, V. Nikitin, S. Watts, Xueti Tang, D. Apalkov","doi":"10.1109/DRC.2010.5551975","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551975","url":null,"abstract":"Non-volatile STT-RAM (spin transfer torque random access memory) is a new memory technology that combines the capacity and cost benefits of DRAM, the fast read and write performance of SRAM and the non-volatility of Flash with essentially unlimited endurance. It has excellent write selectivity, excellent scalability beyond the 45 nm technology node, low power consumption, and a simpler architecture and manufacturing process than first-generation, field-switched MRAM. A magnetic tunnel junction (MTJ) device (Fig. 1) is used as the information storage memory element, and its magneto-resistance is used for information read-out. To make the STT-RAM technology competitive with mainstream semiconductor memories, the writing current has to be reduced so that the MTJ can be switched by a minimum sized CMOS transistor. In this paper, we discuss our approaches and results in writing current reduction; device read and write performances; robustness against read disturb switching and barrier break down; and prospects of scaling to future smaller nodes.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"373 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114966846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551880
J. Nah, Yonghyun Kim, E. Liu, K. Varahramyan, S. Banerjee, E. Tutuc
We report the fabrication and experimental investigation of Ge-SixGe1-x core-shell nanowire (NW) tunneling field effect transistors (TFETs). Low energy ion implantation was used to highly dope the NW TFET source (S) and drain (D). The NW TFETs show ON-state currents of up to ION ∼ 5 µA/µm, and the ambipolar behavior is suppressed by achieving asymmetric doping concentrations at S/D. Furthermore, the NW TFET subthreshold slope (SS) shows little temperature dependence down to 77K, consistent with band-to-band tunneling (BTBT) being the dominant carrier injection mechanism.
{"title":"Ge-SixGe1-x core-shell nanowire tunneling field-effect transistors","authors":"J. Nah, Yonghyun Kim, E. Liu, K. Varahramyan, S. Banerjee, E. Tutuc","doi":"10.1109/DRC.2010.5551880","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551880","url":null,"abstract":"We report the fabrication and experimental investigation of Ge-SixGe1-x core-shell nanowire (NW) tunneling field effect transistors (TFETs). Low energy ion implantation was used to highly dope the NW TFET source (S) and drain (D). The NW TFETs show ON-state currents of up to ION ∼ 5 µA/µm, and the ambipolar behavior is suppressed by achieving asymmetric doping concentrations at S/D. Furthermore, the NW TFET subthreshold slope (SS) shows little temperature dependence down to 77K, consistent with band-to-band tunneling (BTBT) being the dominant carrier injection mechanism.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117048882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551930
K. Tahy, Margaret Jane Fleming, Barbara Raynal, V. Protasenko, S. Koswatta, D. Jena, H. Xing, M. Kelly
The exceptional electrical properties of graphene materials have led to an explosion of research investigating the potential of graphene as the foundation for a future generation of devices as well as developing methods of producing high quality graphene materials. Material quality and our ability to manipulate the properties of graphene will ultimately determine the success of graphene as a device platform. Recently, the formation of single layer graphene via catalyzed-chemical vapor deposition (CVD) on copper foils has generated much interest [1]. A few groups have reported the CVD growth of graphene on copper, and transport properties including quantum Hall effect [2,3] in layers subsequently transferred to insulating substrates. However, there have been no careful studies of FETs fabricated from them. In this work, we report the characteristics of single-layer graphene FETs whose channels were grown by CVD on copper.
{"title":"Device characteristics of single-layer graphene FETs grown on copper","authors":"K. Tahy, Margaret Jane Fleming, Barbara Raynal, V. Protasenko, S. Koswatta, D. Jena, H. Xing, M. Kelly","doi":"10.1109/DRC.2010.5551930","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551930","url":null,"abstract":"The exceptional electrical properties of graphene materials have led to an explosion of research investigating the potential of graphene as the foundation for a future generation of devices as well as developing methods of producing high quality graphene materials. Material quality and our ability to manipulate the properties of graphene will ultimately determine the success of graphene as a device platform. Recently, the formation of single layer graphene via catalyzed-chemical vapor deposition (CVD) on copper foils has generated much interest [1]. A few groups have reported the CVD growth of graphene on copper, and transport properties including quantum Hall effect [2,3] in layers subsequently transferred to insulating substrates. However, there have been no careful studies of FETs fabricated from them. In this work, we report the characteristics of single-layer graphene FETs whose channels were grown by CVD on copper.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121937299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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