{"title":"T-REX，用于大型主机服务器的刀片封装架构","authors":"G. Katopis, W. Becker, H. Harrer","doi":"10.1109/epep.2003.1249988","DOIUrl":null,"url":null,"abstract":"In this paper we describe the application of the blade packaging concept to the z-series of e-servers. The advantages of such packaging architecture are highlighted and the challenges for the system performance are identified. The physical and electrical attributes of the five types of Buses required to support processing operating frequency of 1.2 GHz in an SMP (Symmetric Multi-Processing) architecture with up to 64 PU (Processing Units) are tabulated. The evolution of the I/O circuits for each of these Buses is described along with the Bus cycle time and bandwidth trends.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"T-REX, a blade packaging architecture for mainframe servers\",\"authors\":\"G. Katopis, W. Becker, H. Harrer\",\"doi\":\"10.1109/epep.2003.1249988\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we describe the application of the blade packaging concept to the z-series of e-servers. The advantages of such packaging architecture are highlighted and the challenges for the system performance are identified. The physical and electrical attributes of the five types of Buses required to support processing operating frequency of 1.2 GHz in an SMP (Symmetric Multi-Processing) architecture with up to 64 PU (Processing Units) are tabulated. The evolution of the I/O circuits for each of these Buses is described along with the Bus cycle time and bandwidth trends.\",\"PeriodicalId\":254477,\"journal\":{\"name\":\"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)\",\"volume\":\"38 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/epep.2003.1249988\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/epep.2003.1249988","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
T-REX, a blade packaging architecture for mainframe servers
In this paper we describe the application of the blade packaging concept to the z-series of e-servers. The advantages of such packaging architecture are highlighted and the challenges for the system performance are identified. The physical and electrical attributes of the five types of Buses required to support processing operating frequency of 1.2 GHz in an SMP (Symmetric Multi-Processing) architecture with up to 64 PU (Processing Units) are tabulated. The evolution of the I/O circuits for each of these Buses is described along with the Bus cycle time and bandwidth trends.
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