A high speed subthreshold SRAM cell design

In this paper, we propose a subthreshold SRAM cell structure which can be read differentially. The main advantage of the cell is its high read current while the static noise margin and power consumption are reasonable. The cell is suitable for high performance applications where the speed is of prime concern. To assess the efficiency of the proposed cell, we compare its characteristics to three subthreshold SRAM cell structures recently introduced in the literature. The cells are implemented in both the bulk and SOI-FinFET technologies at the node of 32nm.