{"title":"基于65nm CMOS的30-36.6 GHz低抖动衰减SIL QVCO频率跟踪环,用于5G前端应用","authors":"Jhe‐Wei Li, Wei-Cheng Chen, Ju-Chien Chou, Yu-Cheng Liu, Hong-Yeh Chang","doi":"10.1109/EuMIC48047.2021.00072","DOIUrl":null,"url":null,"abstract":"In this paper, a low jitter degradation subharmonically injection-locked (SIL) quadrature voltage-controlled oscillator (QVCO) with frequency-tracking loop is presented using 65 nm CMOS process for 5G frontend applications. The QVCO is designed using a modified self-injection coupling technique to enhance the quadrature accuracy. An analog-based frequency-tracking loop is employed in the QVCO to adaptively align the control voltage. As the subharmonic number is 4, the locking frequency is from 30 to 36.6 GHz with a 19.6% fractional bandwidth. The phase noise at 1 MHz offset is −130.3 dBc/Hz, and the jitter integrated from 1 kHz to 40 MHz is 8.7 fs with a degradation of within 7 fs. When the temperature is between 20°C and 70°C, the variations of phase noise, jitter, output power are within 2.5 dB, 5 fs, and 1.5 dB, respectively. The quadrature errors are within 0.5 dB and 0.9°.","PeriodicalId":371692,"journal":{"name":"2020 15th European Microwave Integrated Circuits Conference (EuMIC)","volume":"230 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 30-36.6 GHz Low Jitter Degradation SIL QVCO with Frequency-tracking Loop in 65 nm CMOS for 5G Frontend Applications\",\"authors\":\"Jhe‐Wei Li, Wei-Cheng Chen, Ju-Chien Chou, Yu-Cheng Liu, Hong-Yeh Chang\",\"doi\":\"10.1109/EuMIC48047.2021.00072\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a low jitter degradation subharmonically injection-locked (SIL) quadrature voltage-controlled oscillator (QVCO) with frequency-tracking loop is presented using 65 nm CMOS process for 5G frontend applications. The QVCO is designed using a modified self-injection coupling technique to enhance the quadrature accuracy. An analog-based frequency-tracking loop is employed in the QVCO to adaptively align the control voltage. As the subharmonic number is 4, the locking frequency is from 30 to 36.6 GHz with a 19.6% fractional bandwidth. The phase noise at 1 MHz offset is −130.3 dBc/Hz, and the jitter integrated from 1 kHz to 40 MHz is 8.7 fs with a degradation of within 7 fs. When the temperature is between 20°C and 70°C, the variations of phase noise, jitter, output power are within 2.5 dB, 5 fs, and 1.5 dB, respectively. The quadrature errors are within 0.5 dB and 0.9°.\",\"PeriodicalId\":371692,\"journal\":{\"name\":\"2020 15th European Microwave Integrated Circuits Conference (EuMIC)\",\"volume\":\"230 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-01-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 15th European Microwave Integrated Circuits Conference (EuMIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EuMIC48047.2021.00072\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 15th European Microwave Integrated Circuits Conference (EuMIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EuMIC48047.2021.00072","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 30-36.6 GHz Low Jitter Degradation SIL QVCO with Frequency-tracking Loop in 65 nm CMOS for 5G Frontend Applications
In this paper, a low jitter degradation subharmonically injection-locked (SIL) quadrature voltage-controlled oscillator (QVCO) with frequency-tracking loop is presented using 65 nm CMOS process for 5G frontend applications. The QVCO is designed using a modified self-injection coupling technique to enhance the quadrature accuracy. An analog-based frequency-tracking loop is employed in the QVCO to adaptively align the control voltage. As the subharmonic number is 4, the locking frequency is from 30 to 36.6 GHz with a 19.6% fractional bandwidth. The phase noise at 1 MHz offset is −130.3 dBc/Hz, and the jitter integrated from 1 kHz to 40 MHz is 8.7 fs with a degradation of within 7 fs. When the temperature is between 20°C and 70°C, the variations of phase noise, jitter, output power are within 2.5 dB, 5 fs, and 1.5 dB, respectively. The quadrature errors are within 0.5 dB and 0.9°.