Pub Date : 2021-01-10DOI: 10.1109/EuMIC48047.2021.00039
I. Gertman, Run Levinger, S. Bershansky, J. Kadry, G. Horovitz
This paper presents state of the art digitally controlled oscillator (DCO) suitable for the emerging 5G standard. This design utilizes a very compact common-mode resonator “folded” within the primary LC tank minimizing the area of the oscillator while ensuring high performance. The implemented DCO cover 11 to 15.4 GHz, yielding a fractional tuning range (FTR) of 33.3%. When used with a proper frequency generation scheme this DCO can cover both K and Ka band 5G allocated frequencies. Measured phase noise at 1 MHz offset is −108.8 dBc/Hz at 15.4GHz. Consumed power is 5.2 mW from a 0.8 V supply, obtained figure of merit (FoM) is higher than 185.4 dBc/Hz. The design occupies an area of 0.052 mm2.
{"title":"A 33% Tuning Range Cross-Coupled DCO with “Folded” Common Mode Resonator Covering both 5G MMW Bands in 16-nm CMOS FinFet","authors":"I. Gertman, Run Levinger, S. Bershansky, J. Kadry, G. Horovitz","doi":"10.1109/EuMIC48047.2021.00039","DOIUrl":"https://doi.org/10.1109/EuMIC48047.2021.00039","url":null,"abstract":"This paper presents state of the art digitally controlled oscillator (DCO) suitable for the emerging 5G standard. This design utilizes a very compact common-mode resonator “folded” within the primary LC tank minimizing the area of the oscillator while ensuring high performance. The implemented DCO cover 11 to 15.4 GHz, yielding a fractional tuning range (FTR) of 33.3%. When used with a proper frequency generation scheme this DCO can cover both K and Ka band 5G allocated frequencies. Measured phase noise at 1 MHz offset is −108.8 dBc/Hz at 15.4GHz. Consumed power is 5.2 mW from a 0.8 V supply, obtained figure of merit (FoM) is higher than 185.4 dBc/Hz. The design occupies an area of 0.052 mm2.","PeriodicalId":371692,"journal":{"name":"2020 15th European Microwave Integrated Circuits Conference (EuMIC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116605349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-10DOI: 10.1109/EuMIC48047.2021.00021
S. Mahon, Olivia Ell, Leigh E. Milner, Evgeny Kuxa, A. Parker, Melissa C. Gorman, M. Heimlich
A 10-watt X-band GaN power amplifier has been designed as a testbed to study amplifier temperature under a variety of biases and input drive levels using gate-resistance thermometry. Real-time, in-circuit temperature sensing is demonstrated and discussed for a range of biases and input levels.
{"title":"Real-time. In-circuit Temperature Sensing of an X-Band GaN Power Amplifier","authors":"S. Mahon, Olivia Ell, Leigh E. Milner, Evgeny Kuxa, A. Parker, Melissa C. Gorman, M. Heimlich","doi":"10.1109/EuMIC48047.2021.00021","DOIUrl":"https://doi.org/10.1109/EuMIC48047.2021.00021","url":null,"abstract":"A 10-watt X-band GaN power amplifier has been designed as a testbed to study amplifier temperature under a variety of biases and input drive levels using gate-resistance thermometry. Real-time, in-circuit temperature sensing is demonstrated and discussed for a range of biases and input levels.","PeriodicalId":371692,"journal":{"name":"2020 15th European Microwave Integrated Circuits Conference (EuMIC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129317513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-10DOI: 10.1109/EuMIC48047.2021.00013
M. Bao, V. Vassilev, D. Gustafsson, H. Zirath
Two G-band three-stage power amplifiers (PA), a Darlington PA and a stacked PA, are designed and manufactured in 130 nm InP HBT Technology. The stacked PA shows a 70 GHz bandwidth of S21 (from 140 GHz to 210 GHz) with a peak S21 gain of 30 dB. It has a fractional bandwidth (FBW) of 40%. While the Darlington PA demonstrates a 90 GHz bandwidth of S21 (from 130 GHz to 220 GHz) with a peak S21 gain of 20 dB, the FBW of the Darlington PA is 51% which is highest among the G-band PAs. Furthermore, the Darlington PA has a saturated output power, Psat, of 9.6 dBm at 150 GHz, and a power added efficiency (PAE) of 14.7% with a 55 mW de power consumption. The stacked PA has a Psat of 13.4 dBm at 150 GHz, and a PAE of 17.3% with a 108 mW dc power consumption. To authors' knowledge, the stacked PA has the highest PAE among the D/G-band PAs published in the literature.
{"title":"G-band Power Amplifiers in 130 nm InP Technology","authors":"M. Bao, V. Vassilev, D. Gustafsson, H. Zirath","doi":"10.1109/EuMIC48047.2021.00013","DOIUrl":"https://doi.org/10.1109/EuMIC48047.2021.00013","url":null,"abstract":"Two G-band three-stage power amplifiers (PA), a Darlington PA and a stacked PA, are designed and manufactured in 130 nm InP HBT Technology. The stacked PA shows a 70 GHz bandwidth of S21 (from 140 GHz to 210 GHz) with a peak S21 gain of 30 dB. It has a fractional bandwidth (FBW) of 40%. While the Darlington PA demonstrates a 90 GHz bandwidth of S21 (from 130 GHz to 220 GHz) with a peak S21 gain of 20 dB, the FBW of the Darlington PA is 51% which is highest among the G-band PAs. Furthermore, the Darlington PA has a saturated output power, Psat, of 9.6 dBm at 150 GHz, and a power added efficiency (PAE) of 14.7% with a 55 mW de power consumption. The stacked PA has a Psat of 13.4 dBm at 150 GHz, and a PAE of 17.3% with a 108 mW dc power consumption. To authors' knowledge, the stacked PA has the highest PAE among the D/G-band PAs published in the literature.","PeriodicalId":371692,"journal":{"name":"2020 15th European Microwave Integrated Circuits Conference (EuMIC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129641561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-10DOI: 10.1109/EuMIC48047.2021.00031
Xin Xu, S. Schumann, Ali Ferschischi, W. Finger, C. Carta, F. Ellinger
This paper presents a high-gain, dual-band low noise amplifier (LNA) for 5G wireless systems, which supports simultaneous operation at 28 GHz and 38 GHz. The circuit consists of two cascode stages, and is implemented in a 22 nm FD-SOI CMOS technology. To realize the dual-band operation, dual-band matching networks based on transmission lines and capacitors were used. The presented LNA draws a current of 7.1 mA from a 1.6 V supply, which results in a total power consumption of 11.4 mW. The LNA provides a gain of 19.3 dB and 24 dB at 28 GHz and 38 GHz, respectively. At the input of the LNA a dual-band matching network was implemented to obtain a simultaneous noise and power matching at 28 GHz and 38 GHz. The measured noise figure at 28 GHz and 38 GHz is about 5 dB. The presented LNA compares well against previously reported designs by showing one of the highest gain and the lowest power consumption while still having the comparable performance in the other figures of merit. To the best knowledge of the authors, this is the first LNA using dual-band matching technique to support dual-band operation at 5G millimeter-wave bands.
{"title":"A 28 GHz and 38 GHz High-Gain Dual-Band LNA for 5G Wireless Systems in 22 nm FD-SOI CMOS","authors":"Xin Xu, S. Schumann, Ali Ferschischi, W. Finger, C. Carta, F. Ellinger","doi":"10.1109/EuMIC48047.2021.00031","DOIUrl":"https://doi.org/10.1109/EuMIC48047.2021.00031","url":null,"abstract":"This paper presents a high-gain, dual-band low noise amplifier (LNA) for 5G wireless systems, which supports simultaneous operation at 28 GHz and 38 GHz. The circuit consists of two cascode stages, and is implemented in a 22 nm FD-SOI CMOS technology. To realize the dual-band operation, dual-band matching networks based on transmission lines and capacitors were used. The presented LNA draws a current of 7.1 mA from a 1.6 V supply, which results in a total power consumption of 11.4 mW. The LNA provides a gain of 19.3 dB and 24 dB at 28 GHz and 38 GHz, respectively. At the input of the LNA a dual-band matching network was implemented to obtain a simultaneous noise and power matching at 28 GHz and 38 GHz. The measured noise figure at 28 GHz and 38 GHz is about 5 dB. The presented LNA compares well against previously reported designs by showing one of the highest gain and the lowest power consumption while still having the comparable performance in the other figures of merit. To the best knowledge of the authors, this is the first LNA using dual-band matching technique to support dual-band operation at 5G millimeter-wave bands.","PeriodicalId":371692,"journal":{"name":"2020 15th European Microwave Integrated Circuits Conference (EuMIC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131392469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-10DOI: 10.1109/EuMIC48047.2021.00050
Marc Vigneau, M. Ercoli
This paper presents the design approach, realization and measurement results of a compact driver multi-stages 3-way fully integrated Doherty MMIC 60W power amplifier for true dual-band operation using LDMOS technology. Those results are achieved thanks to the Cds cancellation technic for the combiner design to achieve wideband impedance transformation combined with the 3-way DPA architecture to reach high efficiency in deep back-off and reduce load modulation. Through this design a dedicated attention is put to extend PA video bandwidth thanks to integrated passive device to handle simultaneous digital pre-distortion linearization in B1 and B3, 4G/4.5G telecommunication band. This device is highly linear, after digital pre-distortion ACLR of −56dBc are measured for 2cLTe20MHz 8dB PAR spaced by 345MHz at 35dBm, 12dB OBO, while efficiency is above 29%. Moreover, LDMOS technology is a mature process, consequently this MMIC is a reliable low-cost PA solution for mass production in a very compact package.
{"title":"A 2GHz Compact 60W Fully Integrated 3-Way Doherty for Simultaneous Dual-Band Operation","authors":"Marc Vigneau, M. Ercoli","doi":"10.1109/EuMIC48047.2021.00050","DOIUrl":"https://doi.org/10.1109/EuMIC48047.2021.00050","url":null,"abstract":"This paper presents the design approach, realization and measurement results of a compact driver multi-stages 3-way fully integrated Doherty MMIC 60W power amplifier for true dual-band operation using LDMOS technology. Those results are achieved thanks to the Cds cancellation technic for the combiner design to achieve wideband impedance transformation combined with the 3-way DPA architecture to reach high efficiency in deep back-off and reduce load modulation. Through this design a dedicated attention is put to extend PA video bandwidth thanks to integrated passive device to handle simultaneous digital pre-distortion linearization in B1 and B3, 4G/4.5G telecommunication band. This device is highly linear, after digital pre-distortion ACLR of −56dBc are measured for 2cLTe20MHz 8dB PAR spaced by 345MHz at 35dBm, 12dB OBO, while efficiency is above 29%. Moreover, LDMOS technology is a mature process, consequently this MMIC is a reliable low-cost PA solution for mass production in a very compact package.","PeriodicalId":371692,"journal":{"name":"2020 15th European Microwave Integrated Circuits Conference (EuMIC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127660392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-10DOI: 10.1109/EuMIC48047.2021.00019
P. Colantonio, R. Giofré
The design and experimental characterization of a Monolithic Microwave Integrated Circuits (MMICs) Power Amplifiers (PAs) specifically conceived for next generation Ka-band Very High Throughput Satellites (vHTS) are discussed. The chip has been implemented on a commercially available 100 nm gate length Gallium Nitride on Silicon (GaN-Si) process. The design was carried out accounting for the peculiarities of the application, therefore the selection of the devices' bias points and the matching network topologies was driven, and then accomplished, by carefully considering the thermal constraints of the technology, in order to keep the junction temperature of all devices below 160°C. The MMIC, based on a three stage architecture, has been fully characterized from 17.3 GHz to 20.2 GHz. In such a frequency range, it delivers an output power larger than 40 dBm with a power added efficiency peak higher than 40% and 22 dB of gain.
{"title":"A GaN-on-Si MMIC Power Amplifier with 10W Output Power and 35% Efficiency for Ka-Band Satellite Downlink","authors":"P. Colantonio, R. Giofré","doi":"10.1109/EuMIC48047.2021.00019","DOIUrl":"https://doi.org/10.1109/EuMIC48047.2021.00019","url":null,"abstract":"The design and experimental characterization of a Monolithic Microwave Integrated Circuits (MMICs) Power Amplifiers (PAs) specifically conceived for next generation Ka-band Very High Throughput Satellites (vHTS) are discussed. The chip has been implemented on a commercially available 100 nm gate length Gallium Nitride on Silicon (GaN-Si) process. The design was carried out accounting for the peculiarities of the application, therefore the selection of the devices' bias points and the matching network topologies was driven, and then accomplished, by carefully considering the thermal constraints of the technology, in order to keep the junction temperature of all devices below 160°C. The MMIC, based on a three stage architecture, has been fully characterized from 17.3 GHz to 20.2 GHz. In such a frequency range, it delivers an output power larger than 40 dBm with a power added efficiency peak higher than 40% and 22 dB of gain.","PeriodicalId":371692,"journal":{"name":"2020 15th European Microwave Integrated Circuits Conference (EuMIC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128461368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-10DOI: 10.1109/EuMIC48047.2021.00066
P. Kaul, A. Aljarosha, A. B. Smolders, M. Matters-Kammerer, R. Maaskant
In this paper a new multi-step joint-design approach is described for a multi-channel power amplifier integrated with an IC-to-Waveguide transition. The approach enables an optimal impedance match of a waveguide to an integrated-circuit via a contactless transition. Spatial power combining with a non-isolated contactless transition is achieved in the input and output networks of the power amplifier. Simulation results are presented which are in agreement with the joint-design requirements. This methodology enables IC-to-Waveguide integration and provides a suitable approach for mm-wave system integration.
{"title":"Spatial Power Combining and Impedance Matching Silicon IC-to-Waveguide Contactless Transition","authors":"P. Kaul, A. Aljarosha, A. B. Smolders, M. Matters-Kammerer, R. Maaskant","doi":"10.1109/EuMIC48047.2021.00066","DOIUrl":"https://doi.org/10.1109/EuMIC48047.2021.00066","url":null,"abstract":"In this paper a new multi-step joint-design approach is described for a multi-channel power amplifier integrated with an IC-to-Waveguide transition. The approach enables an optimal impedance match of a waveguide to an integrated-circuit via a contactless transition. Spatial power combining with a non-isolated contactless transition is achieved in the input and output networks of the power amplifier. Simulation results are presented which are in agreement with the joint-design requirements. This methodology enables IC-to-Waveguide integration and provides a suitable approach for mm-wave system integration.","PeriodicalId":371692,"journal":{"name":"2020 15th European Microwave Integrated Circuits Conference (EuMIC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115644460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-10DOI: 10.1109/EuMIC48047.2021.00074
G. Bosi, A. Raffo, R. Giofré, V. Vadalà, G. Vannini, E. Limiti
New system architectures oriented to more and more challenging performance for the next generations of mobile devices demand for an accurate design of integrated circuits. The power amplifier is one of the most critical components in an RF system and the need for high performance has focused the designer attention to complex architectures, such as the Doherty power amplifier (DPA). In its most common implementations, the design requires transistor models showing high-accuracy levels under different classes of operation. In this work, we investigate the possibility of achieving the required level of accuracy for the transistor current-generator model using a set of measurements performed under the different classes of operation that mimic realistic device operation and use them for the model optimization. The developed approach is fully validated on a 28-GHz MMIC DPA, showing good agreement with the measured results.
{"title":"Empowering GaN-Si HEMT Nonlinear Modelling for Doherty Power Amplifier Design","authors":"G. Bosi, A. Raffo, R. Giofré, V. Vadalà, G. Vannini, E. Limiti","doi":"10.1109/EuMIC48047.2021.00074","DOIUrl":"https://doi.org/10.1109/EuMIC48047.2021.00074","url":null,"abstract":"New system architectures oriented to more and more challenging performance for the next generations of mobile devices demand for an accurate design of integrated circuits. The power amplifier is one of the most critical components in an RF system and the need for high performance has focused the designer attention to complex architectures, such as the Doherty power amplifier (DPA). In its most common implementations, the design requires transistor models showing high-accuracy levels under different classes of operation. In this work, we investigate the possibility of achieving the required level of accuracy for the transistor current-generator model using a set of measurements performed under the different classes of operation that mimic realistic device operation and use them for the model optimization. The developed approach is fully validated on a 28-GHz MMIC DPA, showing good agreement with the measured results.","PeriodicalId":371692,"journal":{"name":"2020 15th European Microwave Integrated Circuits Conference (EuMIC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125692095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-10DOI: 10.1109/EuMIC48047.2021.00076
F. Strömbeck, Z. He, H. Zirath
In this work a combined duobinary and PAM-3 (Pulse Amplitude Modulation) modulator is designed and fabricated using a 130 nm silicon germanium process. The RF-DAC based duobinary/PAM-3 modulator covers 95 GHz of bandwidth between 35 GHz and 130 GHz and uses three-valued logic. Together with a power detector, high data rate links can be realized without carrier recovery or phase recovery, thus simplifying the overall design. Data rates up to 30 Gbps is demonstrated using duobinary modulation with a symbol error rate (SER) of 6.4 * 10−6. For PAM-3 modulation data rates up to 28 Gbps is demonstrated with a SER of 1.4 * 10−6. The wide bandwidth and high data rate makes it suitable to be used together with a polymer microwave fiber (PMF) for a low cost and robust system, instead of optic fiber.
{"title":"Multi-Gigabit RF-DAC Based Duobinary/PAM-3 Modulator in 130 nm SiGe HBT","authors":"F. Strömbeck, Z. He, H. Zirath","doi":"10.1109/EuMIC48047.2021.00076","DOIUrl":"https://doi.org/10.1109/EuMIC48047.2021.00076","url":null,"abstract":"In this work a combined duobinary and PAM-3 (Pulse Amplitude Modulation) modulator is designed and fabricated using a 130 nm silicon germanium process. The RF-DAC based duobinary/PAM-3 modulator covers 95 GHz of bandwidth between 35 GHz and 130 GHz and uses three-valued logic. Together with a power detector, high data rate links can be realized without carrier recovery or phase recovery, thus simplifying the overall design. Data rates up to 30 Gbps is demonstrated using duobinary modulation with a symbol error rate (SER) of 6.4 * 10−6. For PAM-3 modulation data rates up to 28 Gbps is demonstrated with a SER of 1.4 * 10−6. The wide bandwidth and high data rate makes it suitable to be used together with a polymer microwave fiber (PMF) for a low cost and robust system, instead of optic fiber.","PeriodicalId":371692,"journal":{"name":"2020 15th European Microwave Integrated Circuits Conference (EuMIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122737916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-10DOI: 10.1109/EuMIC48047.2021.00061
Erez Zolkov, Roy Weiss, A. Madjar, E. Cohen
Integrated true time delay cells are usually large in size, and have high relative delay variation. Here, the true time delay N-path topology is explored, where the signal is under-sampled with a number of parallel S/H circuits, and reconstructed and summed after a given time delay. The proposed circuit provides minimum resolution in time delay, while requiring relatively small area and power. The effect of the true time delay is analyzed with a linear periodic time-variant mathematical model, and is verified through measurements. Measurements of 65-nm CMOS chip implementation show up to 2 ns delay for bandwidth of 400 MHz, with maximum delay variation over frequency of 14 ps, delay resolution of 2 ps and power consumption of 9.6 mW.
{"title":"A Low Power Consumption 65-nm CMOS True Time Delay N-path Circuit Achieving 2 ps Delay Resolution","authors":"Erez Zolkov, Roy Weiss, A. Madjar, E. Cohen","doi":"10.1109/EuMIC48047.2021.00061","DOIUrl":"https://doi.org/10.1109/EuMIC48047.2021.00061","url":null,"abstract":"Integrated true time delay cells are usually large in size, and have high relative delay variation. Here, the true time delay N-path topology is explored, where the signal is under-sampled with a number of parallel S/H circuits, and reconstructed and summed after a given time delay. The proposed circuit provides minimum resolution in time delay, while requiring relatively small area and power. The effect of the true time delay is analyzed with a linear periodic time-variant mathematical model, and is verified through measurements. Measurements of 65-nm CMOS chip implementation show up to 2 ns delay for bandwidth of 400 MHz, with maximum delay variation over frequency of 14 ps, delay resolution of 2 ps and power consumption of 9.6 mW.","PeriodicalId":371692,"journal":{"name":"2020 15th European Microwave Integrated Circuits Conference (EuMIC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130580284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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