CMOS集成电路ESD仿真的Spice建模流程

2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD) Pub Date : 2016-09-01 DOI:10.1109/EOSESD.2016.7592553

G. Langguth, A. Ille

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引用次数: 7

摘要

提出了一种基于SPICE的标准模拟仿真环境下ESD验证的仿真流程。模型包含ESD特定的子电路和故障阈值，可根据需要激活。双极操作和寄生路径的触发与实验数据吻合良好。该流程已成功地在实际设计中进行了测试。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Spice modelling flow for ESD simulation of CMOS ICs

A SPICE based simulation flow is proposed for ESD verification in standard analog simulation environment. Models contain ESD specific sub-circuits and failure thresholds which are activated on demand. Good agreement with experimental data is proven including bipolar operation and the triggering of parasitic paths. The flow has been successfully tested on real designs.

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2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)

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