Ahmed S. H. Ahmed, A. Farid, M. Urteaga, M. Rodwell
{"title":"基于双端口技术设计的204GHz堆叠功率放大器","authors":"Ahmed S. H. Ahmed, A. Farid, M. Urteaga, M. Rodwell","doi":"10.23919/EUMIC.2018.8539884","DOIUrl":null,"url":null,"abstract":"We report stacked mm-wave power amplifiers designed by a novel 2-port technique. Two power amplifiers designed into 130-nm InP HBT to verify the technique. The first design (unit cell) biased at 436mW Pdc produces 34.6mW saturated output power with 5.8% PAE at 204GHz. The amplifier has a 13.9dB peak small signal gain at 236GHz and 27 GHz 3–dB bandwidth. The chip size is 0.63mm×0.54mm including the pads. The second design combines two cells in parallel with an additional gain stage. The design consumes 1.18W Pdc and it shows a 63mW saturated output power with 4.8%PAE at 204GHz. The amplifier has a 22.7 dB peak small signal gain at 230GHz and larger than 25GHz 3–dB bandwidth. The chip size is 0.7mm×1.3mm including the pads. The paper reports the first stacked power amplifier designed in a rigorous way at mm-wave frequenices.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"204GHz Stacked-Power Amplifiers Designed by a Novel Two-Port Technique\",\"authors\":\"Ahmed S. H. Ahmed, A. Farid, M. Urteaga, M. Rodwell\",\"doi\":\"10.23919/EUMIC.2018.8539884\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We report stacked mm-wave power amplifiers designed by a novel 2-port technique. Two power amplifiers designed into 130-nm InP HBT to verify the technique. The first design (unit cell) biased at 436mW Pdc produces 34.6mW saturated output power with 5.8% PAE at 204GHz. The amplifier has a 13.9dB peak small signal gain at 236GHz and 27 GHz 3–dB bandwidth. The chip size is 0.63mm×0.54mm including the pads. The second design combines two cells in parallel with an additional gain stage. The design consumes 1.18W Pdc and it shows a 63mW saturated output power with 4.8%PAE at 204GHz. The amplifier has a 22.7 dB peak small signal gain at 230GHz and larger than 25GHz 3–dB bandwidth. The chip size is 0.7mm×1.3mm including the pads. The paper reports the first stacked power amplifier designed in a rigorous way at mm-wave frequenices.\",\"PeriodicalId\":248339,\"journal\":{\"name\":\"2018 13th European Microwave Integrated Circuits Conference (EuMIC)\",\"volume\":\"58 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 13th European Microwave Integrated Circuits Conference (EuMIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/EUMIC.2018.8539884\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/EUMIC.2018.8539884","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
204GHz Stacked-Power Amplifiers Designed by a Novel Two-Port Technique
We report stacked mm-wave power amplifiers designed by a novel 2-port technique. Two power amplifiers designed into 130-nm InP HBT to verify the technique. The first design (unit cell) biased at 436mW Pdc produces 34.6mW saturated output power with 5.8% PAE at 204GHz. The amplifier has a 13.9dB peak small signal gain at 236GHz and 27 GHz 3–dB bandwidth. The chip size is 0.63mm×0.54mm including the pads. The second design combines two cells in parallel with an additional gain stage. The design consumes 1.18W Pdc and it shows a 63mW saturated output power with 4.8%PAE at 204GHz. The amplifier has a 22.7 dB peak small signal gain at 230GHz and larger than 25GHz 3–dB bandwidth. The chip size is 0.7mm×1.3mm including the pads. The paper reports the first stacked power amplifier designed in a rigorous way at mm-wave frequenices.