A VLSI ATM switch architecture for VBR traffic

An Asynchronous Transfer Mode (ATM) switching network must process data at the rates of 155 Mbps and 620 Mbps as per the standard. Such bandwidth requirements have necessitated the realization of efficient switch architectures. In this paper, we propose a novel architecture for the design of a non-blocking, central buffer switch for ATM networks. The central buffer switch architectures described in the literature organize the logical output queues as linked lists of data packets. Thus, dynamic memory allocation involves the manipulation of the read and the write pointers of these linked lists. In the switch architecture proposed in this work, the packets are stored in the data memory and only the packet addresses are stored in a set of First In First Out (FIFO) buffers that form the logical output queues. This approach eliminates the need for memory accesses for the manipulation of linked lists which improves significantly the response time. A 4/spl times/4 prototype switch of the proposed architecture was designed and verified using the Cadence design tools. The prototype was verified to operate at a frequency of 40 MHz yielding a throughput of 12.334 Gbps.