带有模拟相位旋转器的四路3.125 Gb/s/通道收发器

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.992104

Dong Zheng, Xuecheng Jin, E. Cheung, M. Rana, Gengyue Song, Yong Jiang, Y. Sutu, Bin Wu

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引用次数: 20

摘要

一个0.18 /spl mu/m/sup 2/ CMOS四路收发器在200mw /信道消耗下提供12.5 Gb/s的全双工原始数据吞吐量。CDR(时钟/数据恢复)中的模拟相位旋转器消除了数字相位插值技术的量化误差，导致峰值输出抖动<17 ps。

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A quad 3.125 Gb/s/channel transceiver with analog phase rotators

A 0.18 /spl mu/m/sup 2/ CMOS quad transceiver provides 12.5 Gb/s full-duplex raw data throughput at 200 mW/channel consumption. An analog phase rotator in CDR (clock/data recovery) eliminates the quantization error of digital phase interpolation techniques, resulting in <17 ps peak-peak output jitter.

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2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

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