Low-power bufferless resonant clock distribution networks

The major design challenges toward a highly power- efficient bufferless resonant clock distribution network is discussed. The presented discussion is supported by measurements on three different clock distribution networks implemented in a test chip fabricated in 0.13-mum standard CMOS process. In addition to presenting a detailed power comparison between these networks and the conventional buffer-driven scheme, the clock jitter characteristic in bufferless clock distribution is discussed. Furthermore, injection-locking phenomenon is utilized to suppress data- dependent jitter and to achieve a low-jitter clock distribution.