A fast architecture for deblocking filter in H.264/AVC using clock cycles saving process

In this paper a fast architecture for Deblocking Filter in H.264/AVC video coding standard is presented. This architecture consists of a jump circuit which can increase the processing speed. To reduce the system complexity, we consider a single port external memory to be connected to our architecture. Accessing to the external memory is reduced by reusing stored blocks. Filtering operation is concurrent with reading/writing blocks. Simulation results show that the processing cycle count of the proposed architecture has decreased comparing to other similar architectures.