GaP源漏式SOI 1T-DRAM:解决关键技术挑战

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI:10.1109/S3S.2013.6716573

A. Pal, A. Nainani, Z. Ye, X. Bao, E. Sanchez, K. Saraswat

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摘要

提出了一种基于SOI的硅通道GaP源漏1T DRAM。利用基于bjt锁存器的编程，证明了GaP-SD 1T-DRAM的可扩展性可以扩展到20nm。提出了一种降低GaP源极和漏极的片阻和接触电阻的方法。采用镍合金使GaP-SD晶体管的导通电流提高了一个数量级，并建立了良好的可扩展性。

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GaP source-drain SOI 1T-DRAM: Solving the key technological challenges

SOI based GaP source drain 1T DRAM with silicon channel is proposed. Using BJT-latch based programing, it is shown that the scalability of GaP-SD 1T-DRAM can be extended up to 20nm. Nickel alloying of GaP is proposed as a method to reduce the sheet and contact resistance of GaP source and drain. Using nickel alloying, the ON-current of the GaP-SD transistor is improved by an order and the proper scalability behavior is established.

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2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

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