Comparative analysis of adiabatic logics in sub-threshold regime for ultra-low power application

In super-threshold regime, a plethora of adiabatic logic styles are reported for ultra-low power design. In this paper a comparative analysis of transistor based imperative logic styles are analyzed in the sub-threshold regime for the first time in the literature. A uniform test bench is set up for fair comparison. Extensive CADENCE simulations were done using 22nm technology file to analyze the effect of loading, temperature and the supply voltage on power dissipations of the logic styles in sub-threshold regime. Significant differences in workability, power consumption, and logic degradation were found among the various logic styles. Simulation shows that efficient charge recovery logic (ECRL) is efficacious amongst the transistor based adiabatic logic styles in sub-threshold regime.