TLM automation for multi-core design

Transaction Level Models (TLMs) are being increasingly used by multi-core system designers for design validation and embedded SW development. However, with well defined modeling semantics and TLM automation tools, it is also possible to use TLMs for multi-core design. This paper presents recent research in automatic generation of timed TLMs for early, yet reliable, evaluation of multi-core design decisions. The TLMs are automatically generated from a given mapping of a concurrent application to a multi-core platform. The application code is annotated with delays at the basic-block level of granularity. Similarly, the platform services, such as communication and scheduling, also include timing delays. The TLM automation methods have been implemented in the Embedded System Environment (ESE) toolset. Our experimental results with ESE demonstrate that multi-core TLMs can be generated in the order of seconds; they simulate close to host-compiled application execution speed, and are more than 90% accurate compared to board measurements on average for industrial size examples. Therefore, TLM automation enables early and reliable evaluation of multi-core design decisions.