直接数字频率合成器使用高阶多项式近似

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.992149

D. Caro, E. Napoli, A. Strollo

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引用次数: 40

摘要

采用多项式近似法对两个80 MHz 0.35 /spl mu/m 3.3V CMOS无rom DDFS与基于cordic的电路进行了比较。一个60 dBc的SFDR DDFS采用二阶多项式，功率为0.18 mm/sup /，功耗为15mw。一个80 dBc的SFDR DDFS采用三阶多项式和0.44 mm/sup /，功耗为35 mW。

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Direct digital frequency synthesizers using high-order polynomial approximation

Two 80 MHz 0.35 /spl mu/m 3.3V CMOS ROM-less DDFS using polynomial approximation are compared with Cordic-based circuits. A 60 dBc SFDR DDFS uses 2nd-order polynomials and 0.18 mm/sup 2/, with 15 mW dissipation. An 80 dBc SFDR DDFS uses 3rd-order polynomials and 0.44 mm/sup 2/, with 35 mW dissipation.

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2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

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