A Spur-Free Low-Complexity Hybrid Nested Bus-Splitting/SP-MASH Digital Delta-Sigma Modulator

Digital Delta-Sigma Modulators (DDSMs) are widely used in integrated circuits for wireless communications, particularly in fractional-N frequency synthesizers and oversampled digital-to-analog converters (DACs). A large bus-width is often required to have fine frequency resolution especially in 5G, which causes a high hardware complexity. A nested bus-splitting DDSM has advantages of potential speed and compact area over the conventional DDSMs, and hence reduces hardware complexity thanks to its smaller bus width. However, this architecture still suffers from spurious tones, especially in the case of constant or periodic inputs. In this work, an SP-MASH architecture has been embedded into a nested bus-splitting DDSM to overcome the spur problem. The synthesis result by Synopsys Design Compiler using TSMC 28 nm CMOS standard cell shows that the advantage of hardware cost was preserved while the spur-free performance was achieved by this hybrid scheme. Its function and effectiveness was also successfully verified with Xilinx Virtex UltraScale+ field-programmable-gate-array (FPGA).