{"title":"随机多相压控振荡器1.8 GHz CMOS分数n频率合成器","authors":"C. Heng, B. Song","doi":"10.1109/CICC.2002.1012864","DOIUrl":null,"url":null,"abstract":"A synthesizer in 0.6 /spl mu/m CMOS with an on-chip multiphase VCO exhibits no spurs resulting from interpolated phase errors. The proposed architecture randomizes phase errors of the multi-phase VCO to eliminate spurious tones generated by phase mismatch. Phase noise measured at 1.715 GHz is lower than -80 dBc within 20 kHz loop bandwidth and -118 dBc at 1 MHz offset with fractional spur below -70 dBc. The chip consumes 140 mW at 3.3 V and occupies 3.7 mm/spl times/4.6 mm.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"94","resultStr":"{\"title\":\"A 1.8 GHz CMOS fractional-N frequency synthesizer with randomized multi-phase VCO\",\"authors\":\"C. Heng, B. Song\",\"doi\":\"10.1109/CICC.2002.1012864\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A synthesizer in 0.6 /spl mu/m CMOS with an on-chip multiphase VCO exhibits no spurs resulting from interpolated phase errors. The proposed architecture randomizes phase errors of the multi-phase VCO to eliminate spurious tones generated by phase mismatch. Phase noise measured at 1.715 GHz is lower than -80 dBc within 20 kHz loop bandwidth and -118 dBc at 1 MHz offset with fractional spur below -70 dBc. The chip consumes 140 mW at 3.3 V and occupies 3.7 mm/spl times/4.6 mm.\",\"PeriodicalId\":209025,\"journal\":{\"name\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"94\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2002.1012864\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2002.1012864","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1.8 GHz CMOS fractional-N frequency synthesizer with randomized multi-phase VCO
A synthesizer in 0.6 /spl mu/m CMOS with an on-chip multiphase VCO exhibits no spurs resulting from interpolated phase errors. The proposed architecture randomizes phase errors of the multi-phase VCO to eliminate spurious tones generated by phase mismatch. Phase noise measured at 1.715 GHz is lower than -80 dBc within 20 kHz loop bandwidth and -118 dBc at 1 MHz offset with fractional spur below -70 dBc. The chip consumes 140 mW at 3.3 V and occupies 3.7 mm/spl times/4.6 mm.
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