Software Tool Aiding Analysis and Design of Low-Power Parallel Prefix Adders

In this paper, a software tool aiding the design of Parallel Prefix Adders is presented. It supports design of carry generation-propagation block by calculating a circuit activity and equivalent capacitance for the requested input activity behavior. Thanks to a graphical interface, a user can test many possibilities in an easy way by drawing a graph of propagation-generation block. Parameters are calculated and shown on the graph for all nodes. Finally, after checking of the graph completeness, the netlist of the adder is generated. The tool is useful when the designer, looking for the best solution, wants to analyze many adders’ structures for given input activity scenarios.