集成电路版图二维符号压缩的新方法

[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track Pub Date : 1989-01-03 DOI:10.1109/HICSS.1989.47138

Y. Cheng, R. Fujii

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引用次数: 0

摘要

提出了一种二维集成电路符号布局压缩方法。布局元素与选定原点之间的距离被最小化，以实现紧凑的布局。与一维压缩相比，该算法的压缩效果更好，且时间复杂度相同。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A new method for two dimensional symbolic compaction of IC layout

A method for two-dimensional IC symbolic layout compaction is presented. Distances between the layout elements and the selected origin are minimized to achieve a compacted layout. Compared to one-dimensional compaction, this algorithm gets better results and its time complexity is of the same order.<>

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[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track

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