T. Ohnakado, S. Yamakawa, T. Murakami, A. Furukawa, E. Taniguchi, H. Ueda, N. Suematsu, T. Oomori
{"title":"利用耗尽层扩展晶体管(DETs)堆叠晶体管配置的分压效应实现21.5 dBm功率处理5 GHz发射/接收CMOS开关","authors":"T. Ohnakado, S. Yamakawa, T. Murakami, A. Furukawa, E. Taniguchi, H. Ueda, N. Suematsu, T. Oomori","doi":"10.1109/VLSIC.2003.1221152","DOIUrl":null,"url":null,"abstract":"This paper reports for the first time an over-20 dBm power-handling 5 GHz transmit/receive (T/R) CMOS switch. The Depletion-layer-Extended Transistor (DET), which possesses high effective substrate resistance, enables the voltage division effect of the stacked transistor configuration to work in CMOS, thus realizing this high power-handling capability. Furthermore, despite insertion-loss (I/sub L/) degradation due to double on-resistance with the stacked transistor configuration, a receive-mode I/sub L/ (I/sub L/@RX) of as low as 1.44 dB at 5 GHz is accomplished with the benefit of the I/sub L/ improvement effects in the DET, in addition to a very low transmit-mode I/sub L/ (I/sub L/@TX) of 0.95 dB at 5 GHz.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"197 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"21.5 dBm power-handling 5 GHz transmit/receive CMOS switch realized by voltage division effect of stacked transistor configuration with Depletion-layer-Extended Transistors (DETs)\",\"authors\":\"T. Ohnakado, S. Yamakawa, T. Murakami, A. Furukawa, E. Taniguchi, H. Ueda, N. Suematsu, T. Oomori\",\"doi\":\"10.1109/VLSIC.2003.1221152\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper reports for the first time an over-20 dBm power-handling 5 GHz transmit/receive (T/R) CMOS switch. The Depletion-layer-Extended Transistor (DET), which possesses high effective substrate resistance, enables the voltage division effect of the stacked transistor configuration to work in CMOS, thus realizing this high power-handling capability. Furthermore, despite insertion-loss (I/sub L/) degradation due to double on-resistance with the stacked transistor configuration, a receive-mode I/sub L/ (I/sub L/@RX) of as low as 1.44 dB at 5 GHz is accomplished with the benefit of the I/sub L/ improvement effects in the DET, in addition to a very low transmit-mode I/sub L/ (I/sub L/@TX) of 0.95 dB at 5 GHz.\",\"PeriodicalId\":270304,\"journal\":{\"name\":\"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)\",\"volume\":\"197 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2003.1221152\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2003.1221152","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
21.5 dBm power-handling 5 GHz transmit/receive CMOS switch realized by voltage division effect of stacked transistor configuration with Depletion-layer-Extended Transistors (DETs)
This paper reports for the first time an over-20 dBm power-handling 5 GHz transmit/receive (T/R) CMOS switch. The Depletion-layer-Extended Transistor (DET), which possesses high effective substrate resistance, enables the voltage division effect of the stacked transistor configuration to work in CMOS, thus realizing this high power-handling capability. Furthermore, despite insertion-loss (I/sub L/) degradation due to double on-resistance with the stacked transistor configuration, a receive-mode I/sub L/ (I/sub L/@RX) of as low as 1.44 dB at 5 GHz is accomplished with the benefit of the I/sub L/ improvement effects in the DET, in addition to a very low transmit-mode I/sub L/ (I/sub L/@TX) of 0.95 dB at 5 GHz.