Seungyoung Ahn, Jongbae Park, Daehyun Chung, Joungho Kim
{"title":"用封装键合线电感补偿大于Gbps差分SerDes器件的ESD和输入电容效应","authors":"Seungyoung Ahn, Jongbae Park, Daehyun Chung, Joungho Kim","doi":"10.1109/EPEP.2003.1250022","DOIUrl":null,"url":null,"abstract":"We firstly introduce the compensation of ICs input capacitance effect by using the package bondwire inductance. With the analysis of this effect, we suggested the methodology of finding optimized inductance and demonstrated the improvement in time-domain performance by simulation and measurement.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Compensation of ESD and input capacitance effect by using package bondwire inductance for over Gbps differential SerDes devices\",\"authors\":\"Seungyoung Ahn, Jongbae Park, Daehyun Chung, Joungho Kim\",\"doi\":\"10.1109/EPEP.2003.1250022\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We firstly introduce the compensation of ICs input capacitance effect by using the package bondwire inductance. With the analysis of this effect, we suggested the methodology of finding optimized inductance and demonstrated the improvement in time-domain performance by simulation and measurement.\",\"PeriodicalId\":254477,\"journal\":{\"name\":\"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)\",\"volume\":\"117 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-12-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPEP.2003.1250022\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEP.2003.1250022","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Compensation of ESD and input capacitance effect by using package bondwire inductance for over Gbps differential SerDes devices
We firstly introduce the compensation of ICs input capacitance effect by using the package bondwire inductance. With the analysis of this effect, we suggested the methodology of finding optimized inductance and demonstrated the improvement in time-domain performance by simulation and measurement.