不同安装工艺下混合信号CMOS串扰效应分析

V. Ferragina, N. Ghittori, G. Torelli, G. Boselli, G. Trucco, V. Liberali
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引用次数: 2

摘要

本文提出了一种分析混合模拟-数字CMOS集成电路中电压源产生的电流脉冲串扰效应的方法。测试芯片以不同的方式集成和安装,以便比较安装在封装和安装在板上的芯片的测量结果。利用片内和片外寄生的真实模型对该芯片进行了广泛的仿真,研究了当数字开关噪声注入时,模拟部分会发生什么。仿真结果表明,数字块中开关电流的干扰通过互连寄生传播,影响模拟电压,降低电路性能。因此,在混合信号高频电路中,如射频前端,降低互连寄生是至关重要的。测量结果证实了仿真结果
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Analysis of Crosstalk Effects on Mixed-Signal CMOS ICs with Different Mounting Technologies
This paper presents an approach for analysis of crosstalk effects due to current pulses drawn from voltage supplies in mixed analog-digital CMOS integrated circuits. A test chip has been integrated and mounted in different ways, in order to compare measurements on chips mounted in package and mounted on board. The chip has been extensively simulated, using a realistic model of on-chip and off-chip parasitics, to study what happens on the analog section when digital switching noise is injected. Simulations results indicate that disturbances due to switching currents in digital blocks propagate through interconnection parasitics, and affect analog voltages, degrading circuit performance. Therefore, reduction of interconnection parasitics is essential in mixed-signal high-frequency circuits, such as radio-frequency front-ends. Measurements confirm simulation results
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