e-G2C:一种0.14- 8.31µJ/Inference基于神经网络的连续片上自适应处理器,用于异常检测和ECG转换

Yang Zhao, Yongan Zhang, Yonggan Fu, Xuefeng Ouyang, Cheng Wan, Shang Wu, Anton Banta, M. John, A. Post, M. Razavi, Joseph R. Cavallaro, B. Aazhang, Yingyan Lin
{"title":"e-G2C:一种0.14- 8.31µJ/Inference基于神经网络的连续片上自适应处理器,用于异常检测和ECG转换","authors":"Yang Zhao, Yongan Zhang, Yonggan Fu, Xuefeng Ouyang, Cheng Wan, Shang Wu, Anton Banta, M. John, A. Post, M. Razavi, Joseph R. Cavallaro, B. Aazhang, Yingyan Lin","doi":"10.1109/VLSITechnologyandCir46769.2022.9830335","DOIUrl":null,"url":null,"abstract":"This work presents the first silicon-validated dedicated EGM-to-ECG (G2C) processor, dubbed e-G2C, featuring continuous lightweight anomaly detection, event-driven coarse/precise conversion, and on-chip adaptation. e-G2C utilizes neural network (NN) based G2C conversion and integrates 1) an architecture supporting anomaly detection and coarse/precise conversion via time multiplexing to balance the effectiveness and power, 2) an algorithm-hardware co-designed vector-wise sparsity resulting in a 1.6-1.7× speedup, 3) hybrid dataflows for enhancing near 100% utilization for normal/depth-wise(DW)/point-wise(PW) convolutions (Convs), and 4) an on-chip detection threshold adaptation engine for continuous effectiveness. The achieved 0.14-8.31 µJ/inference energy efficiency outperforms prior arts under similar complexity, promising real-time detection/conversion and possibly life-critical interventions.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"e-G2C: A 0.14-to-8.31 µJ/Inference NN-based Processor with Continuous On-chip Adaptation for Anomaly Detection and ECG Conversion from EGM\",\"authors\":\"Yang Zhao, Yongan Zhang, Yonggan Fu, Xuefeng Ouyang, Cheng Wan, Shang Wu, Anton Banta, M. John, A. Post, M. Razavi, Joseph R. Cavallaro, B. Aazhang, Yingyan Lin\",\"doi\":\"10.1109/VLSITechnologyandCir46769.2022.9830335\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work presents the first silicon-validated dedicated EGM-to-ECG (G2C) processor, dubbed e-G2C, featuring continuous lightweight anomaly detection, event-driven coarse/precise conversion, and on-chip adaptation. e-G2C utilizes neural network (NN) based G2C conversion and integrates 1) an architecture supporting anomaly detection and coarse/precise conversion via time multiplexing to balance the effectiveness and power, 2) an algorithm-hardware co-designed vector-wise sparsity resulting in a 1.6-1.7× speedup, 3) hybrid dataflows for enhancing near 100% utilization for normal/depth-wise(DW)/point-wise(PW) convolutions (Convs), and 4) an on-chip detection threshold adaptation engine for continuous effectiveness. The achieved 0.14-8.31 µJ/inference energy efficiency outperforms prior arts under similar complexity, promising real-time detection/conversion and possibly life-critical interventions.\",\"PeriodicalId\":332454,\"journal\":{\"name\":\"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830335\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830335","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

这项工作提出了第一个经过硅验证的专用egm到ecg (G2C)处理器,称为e-G2C,具有连续轻量级异常检测,事件驱动的粗/精确转换和片上适应功能。e-G2C利用基于神经网络(NN)的G2C转换,并集成了1)支持异常检测和通过时间复用进行粗/精确转换的架构,以平衡效率和功率;2)算法-硬件协同设计的矢量稀疏性,从而实现1.6-1.7倍的加速;3)混合数据流,可将正常/深度/点卷积(Convs)的利用率提高近100%。4)片上检测阈值自适应引擎,实现持续有效性。所实现的0.14-8.31 μ J/推理能量效率在类似复杂性下优于现有技术,有望实现实时检测/转换,并可能实现生命关键干预。
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e-G2C: A 0.14-to-8.31 µJ/Inference NN-based Processor with Continuous On-chip Adaptation for Anomaly Detection and ECG Conversion from EGM
This work presents the first silicon-validated dedicated EGM-to-ECG (G2C) processor, dubbed e-G2C, featuring continuous lightweight anomaly detection, event-driven coarse/precise conversion, and on-chip adaptation. e-G2C utilizes neural network (NN) based G2C conversion and integrates 1) an architecture supporting anomaly detection and coarse/precise conversion via time multiplexing to balance the effectiveness and power, 2) an algorithm-hardware co-designed vector-wise sparsity resulting in a 1.6-1.7× speedup, 3) hybrid dataflows for enhancing near 100% utilization for normal/depth-wise(DW)/point-wise(PW) convolutions (Convs), and 4) an on-chip detection threshold adaptation engine for continuous effectiveness. The achieved 0.14-8.31 µJ/inference energy efficiency outperforms prior arts under similar complexity, promising real-time detection/conversion and possibly life-critical interventions.
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