倒装芯片技术:一种提供高密度互连的已知优良芯片的方法

G. Adema, C. Berry, N. Koopman, G. Rinne, E. Yung, I. Turlik
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引用次数: 14

摘要

倒装芯片互连提供了最高的互连密度,这使得该技术对多芯片模块的使用非常有吸引力。然而,有几个因素阻碍了这项技术的使用。这些因素包括碰撞晶圆的可用性,以及在组装到多芯片模块之前无法测试和磨合碰撞芯片。MCNC通过建立晶圆碰撞设备和开发裸模测试和烧蚀方法解决了这两个问题。焊料凸起的形成基于电镀工艺。凸起芯片的测试和烧成是使用一种独特的工艺来完成的,该工艺利用临时冶金附着到测试基板上。下面几节将详细描述这些过程。
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Flip Chip Technology: A Method for Providing Known Good Die with High Density Interconnections
Flip chip interconnections provide the highest interconnection density possible which makes this technology very attractive for use with multichip modules. However, several factors have hindered the use of this technology. These factors include the availability of bumped wafers and the inability to test and bum-in bumped chips before they are assembled onto a multichip module. MCNC has addressed both of these concerns by establishing a wafer bumping facility and by developing a method for the test and burn-in of bare die. The solder bump formation is based upon an electroplating process. The test and burn-in of bumped chips is accomplished using a unique process which utilizes a temporary metallurgical attachment to a test substrate. These processes are described in detail in the following sections.
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