A novel equalizer for the high-loss backplane at Nyquist frequency

The paper presents a small area and low power equalizer for the high-loss serial backplane built in 65 nm CMOS technology. To mitigate the effects of channel loss and other impairments, a programmable continuous time linear equalizer (CTLE) and a programmable 5-tap decision feedback equalizer (DFE) are used in the receiver. In which DFE employs a loop-unrolling structure to meet timing constraints. Furthermore power and area savings are achieved by using two kinds of D-flip-flop (DFF) in proposed DFE and CMOS-style rail-to-rail clocking. The whole equalizer occupies 0.0091 mm2 and consumes 11-mW under a 1.2 V supply when equalizing 6.25 Gb/s data passed over a FR4 PCB channel with 10~28 dB of loss at Nyquist frequency.