{"title":"用于数字音频的立体声异步采样率转换器","authors":"B. Adams, T. Kwan","doi":"10.1109/VLSIC.1993.920529","DOIUrl":null,"url":null,"abstract":"The design of an asynchronous sample-rate converter for digital audio applications is presented. Input and output sample rates are sensed automatically. The converter can be slaved to both input and output sample clocks that need not be synchronous to the chip's master clock. Sample rate ratio changes of up to 2:1 in either direction can be accommodated. Measured output SNR while driven by a 10 kHz 20-bit sine wave is 102 dB. This 200 K transistor chip is fabricated using a 0.8 /spl mu/m CMOS technology. Power dissipation is 150 mW at 16 MHz.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A stereo asynchronous sample-rate converter for digital audio\",\"authors\":\"B. Adams, T. Kwan\",\"doi\":\"10.1109/VLSIC.1993.920529\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The design of an asynchronous sample-rate converter for digital audio applications is presented. Input and output sample rates are sensed automatically. The converter can be slaved to both input and output sample clocks that need not be synchronous to the chip's master clock. Sample rate ratio changes of up to 2:1 in either direction can be accommodated. Measured output SNR while driven by a 10 kHz 20-bit sine wave is 102 dB. This 200 K transistor chip is fabricated using a 0.8 /spl mu/m CMOS technology. Power dissipation is 150 mW at 16 MHz.\",\"PeriodicalId\":127467,\"journal\":{\"name\":\"Symposium 1993 on VLSI Circuits\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-05-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Symposium 1993 on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1993.920529\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Symposium 1993 on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1993.920529","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A stereo asynchronous sample-rate converter for digital audio
The design of an asynchronous sample-rate converter for digital audio applications is presented. Input and output sample rates are sensed automatically. The converter can be slaved to both input and output sample clocks that need not be synchronous to the chip's master clock. Sample rate ratio changes of up to 2:1 in either direction can be accommodated. Measured output SNR while driven by a 10 kHz 20-bit sine wave is 102 dB. This 200 K transistor chip is fabricated using a 0.8 /spl mu/m CMOS technology. Power dissipation is 150 mW at 16 MHz.
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