Issues and Directions for Graphics Hardware Accelerators

Hello, it's a pleasure to be here. I was introduced to graphics by professor James Clark at Stanford University during the summer of 1981. I didn't see much of Jim that summer, however, as he was very busy completing the development of the first Geometry Engine integrated circuit. During some of his little spare time he guided me in the design of an NMOS-based framebuffer controller which could serve as a back-end to a pipe of Geometry Engines in a complete graphics system. While my conceptual framebuffer design was never implemented, Jim asked my to join him and several others in a venture based on the Geometry Engine technology. With Jim in the lead this group founded Silicon Graphics in the summer of 1982, having begun development of a Geometry Engine-based graphics system in the fall of 1981. Thus this talk roughly commemorates my tenth anniversary in the field of graphics. During my ten years I've watched first hand the tremendous growth in both computer and graphics capability. Processors shipped by Silicon Graphics during that period have improved from roughly 1/4 MIP performance (early 68000) to over 250 MIP performance (8 parallel R3000), a ratio of 1000 to 1. Raw graphics performance has increased at an even greater pace, from a few hundred Z-buffered polygons per second in our first machine to over a million in the current offering. And there's no end in sight, of course! The remainder of this talk is a series of brief technical observations, followed by a personal conclusion.