Pub Date : 1991-09-01DOI: 10.2312/EGGH/EGGH91/054-073
Vincent Lefévère, S. Karpf, C. Chaillou, M. Mériaux
The goal of the I.M.O.G.E.N.E. project is to define a real time graphics system. We focus on true real time display, images being computed at frame rate, i.e 50 (or 60) times a second. The I.M.O.G.E.N.E. machine uses no frame buffer. We use a massive object parallelism; the graphics module is made of a large number of object-processors, each one handling one graphics primitive at pixel rate in rasterscan order. Shading computations are made in a deferred shading processor using Phong's method. After a brief presentation of Object-Oriented Architectures, we present new details about the hardware implementation of our Object Processors, and describe for the first time the shading processor.
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Pub Date : 1991-09-01DOI: 10.2312/EGGH/EGGH91/020-033
Oliver Renz, Alwin Gröne
Experiences with the realization of an object processor using a silicon compiler will be described. Object processors are parts of the object oriented display processor architecture PROOF (Pipeline for Rendering in an Object Oriented Framework; [9] and [8]). Placed in an object processor pipeline the object processors perform the scan conversion, the interpolation of the depth values and the normal vectors of the primitive objects of a scene to be rendered. The suitability of the silicon compiler GENESIL for the development of graphics hardware will be examined using the object processor as an example.
本文将描述使用硅编译器实现对象处理器的经验。对象处理器是面向对象显示处理器体系结构PROOF (Pipeline for Rendering in a Object oriented Framework)的一部分。[9]和[8])。放置在一个对象处理器管道中，对象处理器执行扫描转换，深度值的插值和要渲染的场景的基本对象的法向量。将以对象处理器为例，审查硅编译器GENESIL对图形硬件开发的适用性。
{"title":"Silicon Compilers for Graphics Hardware Design?","authors":"Oliver Renz, Alwin Gröne","doi":"10.2312/EGGH/EGGH91/020-033","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH91/020-033","url":null,"abstract":"Experiences with the realization of an object processor using a silicon compiler will be described. Object processors are parts of the object oriented display processor architecture PROOF (Pipeline for Rendering in an Object Oriented Framework; [9] and [8]). Placed in an object processor pipeline the object processors perform the scan conversion, the interpolation of the depth values and the normal vectors of the primitive objects of a scene to be rendered. The suitability of the silicon compiler GENESIL for the development of graphics hardware will be examined using the object processor as an example.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117305430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-09-01DOI: 10.2312/EGGH/EGGH91/009-019
M. Guravage, E. Blake, A. Kuijk
A structural simulator is used both to test hardware and to visualize software that should run on that hardware. In a layered set of graphical hardware simulators, a structural simulator bridges the gap between hardware fidelity on the one side and sufficient performance to visualize graphics algorithms on the other. Essential design requirements were code extensibility and reusability. In order to achieve this, object-oriented methods were adopted. Important design criteria for graphical hardware simulators at this level are that both the exact digital state of the hardware and the graphical output be visualized interactively. The experience with using the XInPosse simulator is presented and analysed. XInPosse simulates a large systolic array in custom VLSI for second order interpolation; in this case to produce shaded scanlines. XInPosse provides the user with a means of tracing commands within the array while interactively setting breakpoints and displaying processors of particular interest. It verified that the hardware could execute the graphics algorithms correctly and that the limitations on numerical accuracy and range were graphically acceptable. An unexpected use was to facilitate communication between chip designers and the graphics researchers. Problems in the documentation of the hardware and workarounds for hardware "bugs" were found more easily through the common reference frame provided by the simulator. It is the intention of the authors to use the modularity provided by the object-oriented design to produce a toolkit for building graphical hardware simulators.
{"title":"XInPosse: Structural Simulation for Graphics Hardware","authors":"M. Guravage, E. Blake, A. Kuijk","doi":"10.2312/EGGH/EGGH91/009-019","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH91/009-019","url":null,"abstract":"A structural simulator is used both to test hardware and to visualize software that should run on that hardware. In a layered set of graphical hardware simulators, a structural simulator bridges the gap between hardware fidelity on the one side and sufficient performance to visualize graphics algorithms on the other. Essential design requirements were code extensibility and reusability. In order to achieve this, object-oriented methods were adopted. Important design criteria for graphical hardware simulators at this level are that both the exact digital state of the hardware and the graphical output be visualized interactively. The experience with using the XInPosse simulator is presented and analysed. XInPosse simulates a large systolic array in custom VLSI for second order interpolation; in this case to produce shaded scanlines. XInPosse provides the user with a means of tracing commands within the array while interactively setting breakpoints and displaying processors of particular interest. It verified that the hardware could execute the graphics algorithms correctly and that the limitations on numerical accuracy and range were graphically acceptable. An unexpected use was to facilitate communication between chip designers and the graphics researchers. Problems in the documentation of the hardware and workarounds for hardware \"bugs\" were found more easily through the common reference frame provided by the simulator. It is the intention of the authors to use the modularity provided by the object-oriented design to produce a toolkit for building graphical hardware simulators.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121300661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-09-01DOI: 10.2312/EGGH/EGGH91/037-053
H. Selzer
Interactive 3D graphics applications require significant arithmetic processing to meet the ever-inreasing desire for higher image complexity and higher resolution in displayed images. This paper describes a graphics processor architecture with a high degree of parallelism connected to a distributed frame buffer. The architecture can be configured with an arbitrary number of identical, high level programmable processors operating in parallel. Within the architecture an automatic load balancing mechanism is presented which distributes the processing load between geometry and rendering section. After the unique features of the architecture are described the load balancing mechanism is analyzed and the increase of performance is demonstrated.
{"title":"Dynamic Load Balancing within a High Performance Graphics System","authors":"H. Selzer","doi":"10.2312/EGGH/EGGH91/037-053","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH91/037-053","url":null,"abstract":"Interactive 3D graphics applications require significant arithmetic processing to meet the ever-inreasing desire for higher image complexity and higher resolution in displayed images. \u0000 \u0000This paper describes a graphics processor architecture with a high degree of parallelism connected to a distributed frame buffer. The architecture can be configured with an arbitrary number of identical, high level programmable processors operating in parallel. \u0000 \u0000Within the architecture an automatic load balancing mechanism is presented which distributes the processing load between geometry and rendering section. \u0000 \u0000After the unique features of the architecture are described the load balancing mechanism is analyzed and the increase of performance is demonstrated.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134548295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-09-01DOI: 10.2312/EGGH/EGGH91/077-085
D. Cohen-Or, R. Bakalash
This paper presents the conveyor, an interconnection device which operates on a 3D skewed memory space and provides the capability of parallel volumetric transformation. The special concept of the conveyor, its design and implementation are discussed.
{"title":"The Conveyor - an Interconnection Device for Parallel Volumetric Transformations","authors":"D. Cohen-Or, R. Bakalash","doi":"10.2312/EGGH/EGGH91/077-085","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH91/077-085","url":null,"abstract":"This paper presents the conveyor, an interconnection device which operates on a 3D skewed memory space and provides the capability of parallel volumetric transformation. The special concept of the conveyor, its design and implementation are discussed.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127638569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-09-01DOI: 10.2312/EGGH/EGGH91/003-005
K. Akeley
Hello, it's a pleasure to be here. I was introduced to graphics by professor James Clark at Stanford University during the summer of 1981. I didn't see much of Jim that summer, however, as he was very busy completing the development of the first Geometry Engine integrated circuit. During some of his little spare time he guided me in the design of an NMOS-based framebuffer controller which could serve as a back-end to a pipe of Geometry Engines in a complete graphics system. While my conceptual framebuffer design was never implemented, Jim asked my to join him and several others in a venture based on the Geometry Engine technology. With Jim in the lead this group founded Silicon Graphics in the summer of 1982, having begun development of a Geometry Engine-based graphics system in the fall of 1981. Thus this talk roughly commemorates my tenth anniversary in the field of graphics. During my ten years I've watched first hand the tremendous growth in both computer and graphics capability. Processors shipped by Silicon Graphics during that period have improved from roughly 1/4 MIP performance (early 68000) to over 250 MIP performance (8 parallel R3000), a ratio of 1000 to 1. Raw graphics performance has increased at an even greater pace, from a few hundred Z-buffered polygons per second in our first machine to over a million in the current offering. And there's no end in sight, of course! The remainder of this talk is a series of brief technical observations, followed by a personal conclusion.
{"title":"Issues and Directions for Graphics Hardware Accelerators","authors":"K. Akeley","doi":"10.2312/EGGH/EGGH91/003-005","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH91/003-005","url":null,"abstract":"Hello, it's a pleasure to be here. I was introduced to graphics by professor James Clark at Stanford University during the summer of 1981. I didn't see much of Jim that summer, however, as he was very busy completing the development of the first Geometry Engine integrated circuit. During some of his little spare time he guided me in the design of an NMOS-based framebuffer controller which could serve as a back-end to a pipe of Geometry Engines in a complete graphics system. While my conceptual framebuffer design was never implemented, Jim asked my to join him and several others in a venture based on the Geometry Engine technology. With Jim in the lead this group founded Silicon Graphics in the summer of 1982, having begun development of a Geometry Engine-based graphics system in the fall of 1981. Thus this talk roughly commemorates my tenth anniversary in the field of graphics. During my ten years I've watched first hand the tremendous growth in both computer and graphics capability. Processors shipped by Silicon Graphics during that period have improved from roughly 1/4 MIP performance (early 68000) to over 250 MIP performance (8 parallel R3000), a ratio of 1000 to 1. Raw graphics performance has increased at an even greater pace, from a few hundred Z-buffered polygons per second in our first machine to over a million in the current offering. And there's no end in sight, of course! The remainder of this talk is a series of brief technical observations, followed by a personal conclusion.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123267435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-01DOI: 10.2312/EGGH/EGGH88/141-170
J. Jayasinghe, A. Kuijk, L. Spaanenburg
In [3] and [1] a new architecture for a Computer Image Generating (CIG) system designed to have optimal Interaction support for realistlc 3D graphics has been presented. There it was stated that -- from an interaction point of viewthere is no need to have access to an image representation as low as the pixel level. This and the fact that the performance and resolution to a major extend has been limited by the pixel update speed enforced by memory technologies. led us to the conclusion that it should be investigated whether a CRT display could be refreshed from an object-level representation of the frame instead of the conventional pixel-level frame store. In this paper we present as a result of this study an architecture of a (multi-processor) Display Controller that is capable to directly refresh a raster display from such an object-level frame representation.
{"title":"A Display Controller for an Object-level Frame Store System","authors":"J. Jayasinghe, A. Kuijk, L. Spaanenburg","doi":"10.2312/EGGH/EGGH88/141-170","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH88/141-170","url":null,"abstract":"In [3] and [1] a new architecture for a Computer Image Generating (CIG) system designed to have optimal Interaction support for realistlc 3D graphics has been presented. There it was stated that -- from an interaction point of viewthere is no need to have access to an image representation as low as the pixel level. This and the fact that the performance and resolution to a major extend has been limited by the pixel update speed enforced by memory technologies. led us to the conclusion that it should be investigated whether a CRT display could be refreshed from an object-level representation of the frame instead of the conventional pixel-level frame store. \u0000 \u0000In this paper we present as a result of this study an architecture of a (multi-processor) Display Controller that is capable to directly refresh a raster display from such an object-level frame representation.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124826885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-01DOI: 10.2312/EGGH/EGGH88/103-117
G. Jense, D. P. Huijsmans
We describe some of our experiences with the implementation of a 3D reconstruction system for the visualization of the shapes and structural development of biological objects. We use a binary voxel model as volumetric representation of the reconstructed objects. The manipulation and display of volumetric representations involve the processing of huge amounts of data, making hardware support a virtual necessity. Instead of attempting to design special purpose hardware, we decided to try and exploit readily available image processing hardware. We use one of the available frame buffers for storage and direct display of the binary voxel data set. The other frame buffer holds either a surface normal view, a depth-shaded pre-image or the binary voxel data set of a secondary object. Altering the light direction or shading function is performed by manipulating the hardware output lookup tables. An additional frame processor is employed for running various filter operators over pre-images, computing bitwise logical functions on two binary voxel data sets and for pan and zoom operations.
{"title":"Hardware Support for the Display and Manipulation of Binary Voxel Models","authors":"G. Jense, D. P. Huijsmans","doi":"10.2312/EGGH/EGGH88/103-117","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH88/103-117","url":null,"abstract":"We describe some of our experiences with the implementation of a 3D reconstruction system for the visualization of the shapes and structural development of biological objects. We use a binary voxel model as volumetric representation of the reconstructed objects. \u0000 \u0000The manipulation and display of volumetric representations involve the processing of huge amounts of data, making hardware support a virtual necessity. Instead of attempting to design special purpose hardware, we decided to try and exploit readily available image processing hardware. \u0000 \u0000We use one of the available frame buffers for storage and direct display of the binary voxel data set. The other frame buffer holds either a surface normal view, a depth-shaded pre-image or the binary voxel data set of a secondary object. Altering the light direction or shading function is performed by manipulating the hardware output lookup tables. An additional frame processor is employed for running various filter operators over pre-images, computing bitwise logical functions on two binary voxel data sets and for pan and zoom operations.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121272793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-01DOI: 10.2312/EGGH/EGGH88/003-017
Andrew D. Nimmo, P. Lister, R. L. Grimsdale
The tools available for ASIC design now offer the features and functionality necessary to permit ideas to be realised in silicon in a relatively short period of time, This paper introduces work undertaken at Sussex University intended to lead to a more complete VLSI Design Strategy, using ECAD packages provided by Mentor Graphics. In particular. it focuses on the use of Behavioural simulation tools and includes a worked example.
{"title":"A VLSI Design Strategy for Graphics","authors":"Andrew D. Nimmo, P. Lister, R. L. Grimsdale","doi":"10.2312/EGGH/EGGH88/003-017","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH88/003-017","url":null,"abstract":"The tools available for ASIC design now offer the features and functionality necessary to permit ideas to be realised in silicon in a relatively short period of time, This paper introduces work undertaken at Sussex University intended to lead to a more complete VLSI Design Strategy, using ECAD packages provided by Mentor Graphics. In particular. it focuses on the use of Behavioural simulation tools and includes a worked example.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"240 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131857181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-10-01DOI: 10.2312/EGGH/EGGH87/133-136
P. Winser
The design of graphics IC's for the consumer market has performance limitations imposed by the need to maintain low cost, and must be driven by consideration of the potential applications. The likely requirements for a consumer aimed real time 3D graphics system are stated in terms of performance and rendering techniques, and a research prototype of a 3D display processor is presented. The processor performs polygon drawing with smooth shading, Z buffer, and texture mapping into standard memory components. Limitations of the system and necessary image quality improvements are discussed.
{"title":"3D Graphics for Consumer Applications: How Realistic Does it Have to Be?","authors":"P. Winser","doi":"10.2312/EGGH/EGGH87/133-136","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH87/133-136","url":null,"abstract":"The design of graphics IC's for the consumer market has performance limitations imposed by the need to maintain low cost, and must be driven by consideration of the potential applications. The likely requirements for a consumer aimed real time 3D graphics system are stated in terms of performance and rendering techniques, and a research prototype of a 3D display processor is presented. The processor performs polygon drawing with smooth shading, Z buffer, and texture mapping into standard memory components. Limitations of the system and necessary image quality improvements are discussed.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"242 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116207790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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