A 130nm PMOS drain-degenerated ratioless level-shifter for near-threshold designs

We present a modified type-I level-up shifter with improved Process-Voltage-Temperature (PVT) robustness, propagation delay and energy consumption. Compared to a standard cross-coupled level-shifter, the circuit comprises a couple of long channel parallel P and N transistors to implement larger PMOS on-resistance maintaining unvaried upstream logic fan-out. Simulation results show significant robustness increase with respect to a standard topology maintaining low NMOS-to-PMOS sizing. Switching energy consumption is reduced from ~ 10pJ to 200fJ and propagation delay from ~ 240ns to 1ns. With Monte Carlo process variation simulations we have verified a reduction in output delay sensitivity from 209ns to 333ps while with transient noise simulation jitter is reduced from 3.5ns to 36ps. Operating ranges are wider in the proposed circuit, while sensitivity to temperature is comparable for high values. A prototype of this drain-degenerated logic-translator has been fabricated in a 130nm CMOS technology and evaluated with measurements.