{"title":"多比特数据总线的拓扑路由","authors":"G. Persky, L. Tran","doi":"10.1109/DAC.1984.1585880","DOIUrl":null,"url":null,"abstract":"In LSI and VLSI layout, certain categories of signal nets, e.g. critical nets, power buses and data buses, require special attention during routing. In data bus routing the goal is to maximize the commonality of the routing paths comprising the bus, without unnecessarily lengthening individual routing paths. A topological data bus router has been implemented in the Hughes Automated Layout system and is the subject of this paper.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"Topological Routing of Multi-Bit Data Buses\",\"authors\":\"G. Persky, L. Tran\",\"doi\":\"10.1109/DAC.1984.1585880\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In LSI and VLSI layout, certain categories of signal nets, e.g. critical nets, power buses and data buses, require special attention during routing. In data bus routing the goal is to maximize the commonality of the routing paths comprising the bus, without unnecessarily lengthening individual routing paths. A topological data bus router has been implemented in the Hughes Automated Layout system and is the subject of this paper.\",\"PeriodicalId\":188431,\"journal\":{\"name\":\"21st Design Automation Conference Proceedings\",\"volume\":\"45 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1984-06-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"21st Design Automation Conference Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DAC.1984.1585880\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"21st Design Automation Conference Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DAC.1984.1585880","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In LSI and VLSI layout, certain categories of signal nets, e.g. critical nets, power buses and data buses, require special attention during routing. In data bus routing the goal is to maximize the commonality of the routing paths comprising the bus, without unnecessarily lengthening individual routing paths. A topological data bus router has been implemented in the Hughes Automated Layout system and is the subject of this paper.
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